mpw-001/foundrympw-001/slot-001peripheral-maxsram: Caravel management SoC attached to the largest possible SRAM that can fit the user's area.mpw-001/slot-002peripheral-vdp-lite: VGA sprite generator.mpw-001/slot-003SoC-softshell: Multicore RISC-V MCU for developing software defined peripherals.mpw-001/slot-004analog-spike-neuron: A 10 bit DAC and an analog neural network neuron.mpw-001/slot-005SoC-sha3: SoC targetted at SHA-3 cryptomining.mpw-001/slot-006peripheral-spectrometer: A digital spectrometer SoC consisting of the SDF-FFT and its support circuitry.mpw-001/slot-007SoC-ibtida: SoC built around Buraq-Mini, a RISC-V based 5 stage pipelined core.mpw-001/slot-008SoC-hs32: HS32 RISC CPU and peripherals.mpw-001/slot-009test-astria: Test circuits for stochastic computation, namely the synthesizable comparators for a stochastic ADC.mpw-001/slot-010SoC-pyfive: SoC testing peripherals for future SoC targeting Micro/Circuit Python.mpw-001/slot-011test-ls130: Test of the Libresilicon generated standard cell library, LS130.mpw-001/slot-012peripheral-mph: Test of building a multi-project-harness inside the user project area.mpw-001/slot-013peripheral-rapcore: Robotic Application Processing Core targetted at motor and motion controller.mpw-001/slot-014test-morphlelogic: Test of Mophle Logic reconfigurable hardware.mpw-001/slot-015peripheral-prng: A pseudo random number generator oriented towards random cache placement and replacement for critical real-time processors.mpw-001/slot-016analog-amsat: 1.3-3.6 GHz Fractional-N Phase Locked Loop and Bandgap reference aimed at Amatuer Radio Satellite Transceiver.mpw-001/slot-017fpga-sofa-hd: Skywater Opensource FPGA (SOFA) - High Density Designmpw-001/slot-018SoC-ghazi: SoC designed by Micro Electronics Research Laboratory in Pakistan.mpw-001/slot-019analog-opamp-fulgor: Operational amplifier (opamp) based on the Miller topology.mpw-001/slot-020SoC-qrib: SoC build around a RISC-V Processor instrumented for learning.mpw-001/slot-021SoC-featherweight: SoC built around the Featherweight CPU and support peripherals.mpw-001/slot-022peripheral-opentdc: Time to Digital Converter (TDC) and a Fine Delay (FD) design.mpw-001/slot-023analog-ota-ldo-vco: Analog and RF circuits including, 5 transistor OTA with trimming resistors to adjust bias, LDO and VCO at 2.45GHz for BT, WiFi applications.mpw-001/slot-024peripheral-fault-spm: 32-bit serial parallel multiplier with design-for-testability (DFT) structures.mpw-001/slot-025peripheral-decred-miner: Blockchain-based cryptocurrency that utilizes a hybrid Proof-of-Work (PoW) and Proof-of-Stake (PoS) mining system.mpw-001/slot-026SoC-microwatt: Microwatt, a 64bit OpenPOWER core.mpw-001/slot-027SoC-6502: An 8bit processor based on the MOS 6502.mpw-001/slot-028SoC-el2: SoC built around N5 (RV32IC) CPU including peripherals.mpw-001/slot-029peripheral-aes: AES accelerator peripheral core.mpw-001/slot-030fpga-sofa-open: Skywater Opensource FPGA (SOFA) hardened using entirely open source flow (OpenLANE).mpw-001/slot-031SoC-Ibex: SoC built around Ibex CPU with AHB-Lite connected peripherals.mpw-001/slot-032SoC-nfive32: SoC built around N5 (RV32IC) CPU to validate several open-source IPs.mpw-001/slot-033peripheral-linsorter: A digital linear insertion sorter accelerator.mpw-001/slot-034fpga-fpga250: FPGA250 is an FPGA designed by UC Berkeley's CS250 class of Fall 2020 and includes a 4x3 grid of CLBs, a multiply-accumulate unit and flexibly-shaped SRAM block.mpw-001/slot-035peripheral-crypto-vga: AES128/256 accelerator core and a VGA graphics/game demo.mpw-001/slot-036fpga-sofa-qlhd: Skywater Opensource FPGA (SOFA) - QLHD Designmpw-001/slot-037analog-collection: Collection of analog circuits including LVDS receiver, ring oscillator, differential VCO, power amplifier and folded cascode opamp.mpw-001/slot-038peripheral-dsp48dac: An experimental W2W DAC and 25x16, 48 MACC DSP block.mpw-001/slot-039fpga-sofa-chd: Skywater Opensource FPGA (SOFA) - CHD Designmpw-001/slot-040SoC-osu: Single-cycle RISC-V processor developed by OSU.mpw-002/foundrympw-002/slot-001AXI DMA using Spinal HDL: This is a DMA controller with AMBA AXI4 interface.mpw-002/slot-002Wishbone CAN: An implementation of a CAN bus controller as a wishbone peripheral for the open MPW shuttle.mpw-002/slot-003Analog Neuron: Analog implementation of the artificial Neuron used in neural networks.mpw-002/slot-004caravel_dsp2: DSP Functions.mpw-002/slot-005FABulous_Sky: Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.mpw-002/slot-006Opencryo_testchip: NMOS and PMOS array, ring oscillator and inductor for cryogenic characterization.mpw-002/slot-007YiFive (Risc V Based SOC): 32 Bit Risc SOC Design with Quad SPI , 8 bit SDRAM Controller , UART, I2C Master and USB 1.1 Host.mpw-002/slot-008Lexicon: This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions.mpw-002/slot-009UCSC OpenRAM Test Chip: Test chip for single and dual port memories created by OpenRAM.mpw-002/slot-010YONGA-LZ4 Decoder: YONGA-LZ4 Decoder Is An Implementation Of The Decoder Of The Popular Lz4 Compression Algorithm.mpw-002/slot-011Potentiometric_Di...: The project aims to design a 10-bit Potentiometric Digital to Analog Converter(DAC).mpw-002/slot-012FuseRISC: FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric for tensorflow micro applications.mpw-002/slot-013Amsat TXRX IC MPW2: This step in the development and prototyping of the Amateur Radio Satellite Transceiver project contains: 150 MSPS differential current steering DAC with dynamic element matching 8 GHz differential Colpitts topology VCO Baseband to IF mixer High-speed buffer amplifier RF IO driver which can be combined with an off-chip distributed balun to drive off chip loads.mpw-002/slot-014Comparator VCO...: Comparator at 3v3 Supply Voltage Voltage Controlled Oscillator with 7 stage ring oscillator (120 MHz to 350 MHz).mpw-002/slot-015Caravel_Multi_encoder: Multi purpose integrated encoder.mpw-002/slot-016Kasirgalabs UART: Simple UART controller.mpw-002/slot-017mpw-002/slot-018uqab: uqab is an SoC.mpw-002/slot-019mpw-002/slot-020caravel_dsc: Caravel Harness based Digital Signal Controller for Embedded Control applications , the user project area has PTC (PWM , Timer and Input Capture) , PID controller , I2C and RTC.mpw-002/slot-021SOFA Plus FPGA: SOFA (Skywater Opensource FPGAs) are a series of open-source FPGA IPs using the open-source Skywater 130nm PDK and OpenFPGA framework.mpw-002/slot-022darkriscv in openlane: The project is a realization of darkriscv processor using openlane and skywater pdk.mpw-002/slot-023General_Purpose_B...: A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is independent of Temperature and Supply variations.mpw-002/slot-024multi project harness v2: saves space on the shuttle by aggregating up to 16 designs in one submission.mpw-002/slot-025Fast GCD for...: Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.mpw-002/slot-026Columbus: Analog Test Chip Consisting of the following: LDO, Load Switch, Bandgap Reference, and an OpAmp.mpw-002/slot-027Space_Shuttle: The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing process and Open Source PDK, as well as to evaluate different reliability mitigation techniques.mpw-002/slot-028Subservient: ASIC adaption of SERV, the award-winning bit serial RISC-V processor.mpw-002/slot-029caravel_analog_fulgor: Analog test chip with master's thesis prototypes: - 1GHz Current Starved VCO - Residual amplifier with gain and variable output common mode.mpw-002/slot-030Bandgap_Reference_Design: A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To Temperature And Supply Voltage Variations.mpw-002/slot-031RenML: A small, Convolutional Neural Network Accelerator on a wishbone slave for Raven Core in Caravel SoC.mpw-002/slot-032io_expander: A gpio expander for the caravel harness to realize a small microcontroller.mpw-002/slot-033Digital PLL: Integer Digitall PLL + LDO + Bandgap + Error Amplifier Design.mpw-002/slot-034multi project harness v2: saves space on the shuttle by aggregating up to 16 designs in one submission.mpw-002/slot-035Caravel_FPU: Caravel_FPU integrates floating point unit with Caravel Core.mpw-002/slot-036BrqRV_EB1: BrqRV EB1 is a machine-mode (M-mode) only, 32-bit CPU small core which supports RISC-V’s integer (I), compressed instruction (C), multiplication and division (M), and instruction-fetch fence, and CSR extensions.mpw-002/slot-037Hilas Analog...: Analog std cells and test structures for audio processing and analog computing.mpw-002/slot-038vlsi-sky130-analo...: First try at open mpw: simple analog circuits.mpw-002/slot-039SHA1 engine: The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR values.mpw-002/slot-040OpenFASOC: This testchip is a demonstrator of our automated analog generators within an SoC implementation.mpw-003/foundrympw-003/slot-001StdCellLib: This is a testwafer project with standard cells that were automatically generated by the Libresilicon StdCellLib generator.mpw-003/slot-0021V8 LDO Design...: 1V8 LDO Design in Skywaters 130nm.mpw-003/slot-003mpw-003/slot-004Zero to ASIC...: MPW3 submission.mpw-003/slot-005Crypto Accelerator v2: SHA/AES accelerator and VGA graphics demo.mpw-003/slot-006picorF0: CAN bus controller and teaching-oriented CPU core.mpw-003/slot-007Randsack: Random number generators, PUFs, and resubmission of MPW-1 Softshell.mpw-003/slot-008YONGA-100M Ethernet: YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.mpw-003/slot-009Approximate Multiplier: This project is implementation of approximate multiplier published in ACM TODAES journal 2021, titled 'Energy Efficient Error Resilient Multiplier Using Low-power Compressors'.mpw-003/slot-010VSD SRAM: Aims at design of a SRAM cell array with a configuration of 1.mpw-003/slot-011Key Value store: Key value store implemented on asic.mpw-003/slot-012MBIST Controller: MBIST controller with Row Redundancy Support.mpw-003/slot-013Riscduino: Arduino compatible Risc-V Based SOC.mpw-003/slot-014caravel_periphera...: A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO , WS281B led controller to the Caravel SoC via the wishbone bus.mpw-003/slot-015UCSC OpenRAM Test Chip v2: This project contains a test chip for several OpenRAM memory configurations.mpw-003/slot-016Class-D Audio Amplifier: This project is intended to implement a closed-loop class-d audio amplifier with 1.mpw-003/slot-017Efabless processor: Basic design to familiarize with this service.mpw-003/slot-018ToolTest gpioCtrl: Digital test design with simple GPIO control for toolchain testing.mpw-003/slot-019Comparator and...: 3v3 comparator with 1v8 output.mpw-003/slot-020Current Starved...: This project focuses on design of a Current Starved VCO using Google Skywater (sky130) Technology node with operating voltage of 1.mpw-003/slot-021Two Stage CMOS...: Two Stage CMOS Operational Amplifier.mpw-003/slot-022Sziklai Pair Amplifier: This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130) Technology node with operating voltage of 1.mpw-003/slot-023Two Stage CMOS...: CMOS OPAMP is Basic building block of analog and Mixed signal circuits.mpw-003/slot-024Pre-Trained...: This project implements a pre-trained neural network for hand-written digits from MNIST dataset.mpw-003/slot-025ROTFPGA: A reconfigurable logic circuit made of identical rotatable tiles.mpw-003/slot-026TreePRAM: Implements a version of the parallel random-access machine used in theoretical computer science courses with a memory sharing model based on a binary tree of processor cores.mpw-003/slot-027TreePRAM-red: Reduced version of TreePRAM for faster builds and tests. Not submitting for the shuttle.mpw-003/slot-028caravel_jacaranda-8: PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!.mpw-003/slot-029Sudoku Accelerator: Sudoku accelerator module that is capable of running an 'only candidate' pass in 23 cycles and a 'naked singles' pass in 108 cycles.mpw-003/slot-030Fixed2Float_Converter: This project is implementation for conversion of 19bit fixed point number to single precision IEEE floating point number.mpw-003/slot-031High Speed Adder: This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.mpw-003/slot-032My_Proj: Nahh.mpw-003/slot-033PWM_Test: nahhhh.mpw-003/slot-034Elpis Light processor: This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle in-order processor based on RISC-V architecture, mixed with some MIPS ideas.mpw-003/slot-035VSDBabySoC: VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.mpw-003/slot-036VSDMemSoC: VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM Instruction Memory (IMem) to separate the processor core and the IMem.mpw-003/slot-037Caravel SRAM Test: The project instantiates an SRAM block in the user project area for testing.mpw-003/slot-0388-bit SAR-ADC...: This is a Analog to Digital Converter based on the popular SAR architecture.mpw-003/slot-039Caravel HyperRAM...: Project instantiates HyperRAM driver for external memory chip (8MB version) and additional OpenRAM 1kB block (32x256B).mpw-003/slot-040Caravel: A template SoC for Google sponsored Open MPW shuttles for SKY130.mpw-004/foundrympw-004/slot-001Zero to ASIC...: Designs from the Zero to ASIC course.mpw-004/slot-002Zero to ASIC...: Re-hardened MPW2 group submission to fix clock issues and re-submit for MPW4.mpw-004/slot-003CMOS only...: Sub 1-V voltage supply, 3.mpw-004/slot-004pifive-soc: RISC-V SoC.mpw-004/slot-005RAM_Generator: This project is for the testing purpose.mpw-004/slot-006Space Controller: This design is a radiation tolerant UART server that can be used for low level control of multiple input/output ports during a radiation testing campaign.mpw-004/slot-007Randsack B1: Random number generators and PUFs.mpw-004/slot-0084T1R Testchip: RRAM testchip designed to evaluate 4t1r configuration.mpw-004/slot-009YONGA-Turbo Encoder: YONGA-Turbo Encoder is an implementation of a high-performance forward error correction (FEC) coding technique.mpw-004/slot-010ICESOC: Ibex Crypto eFPGA SoC.mpw-004/slot-011Key Value store 2: A key value store using a wishbone interface, developed using migen.mpw-004/slot-012Subservient-MPW4: An ASIC-adapted version of the award-winning bit-serial RISC-V processo SERV, resubmitted due to expected issues with mpw2.mpw-004/slot-013Logic BIST: Logic BIST with Scan Chain to detect struck at fault.mpw-004/slot-014riscduino-R1: A arduino pin compatible RISC V Project.mpw-004/slot-015mpw-004/slot-016mpw-004/slot-017CMOS Frequency...: 2.87 GHz frequency synthesizer with programmable sweep.mpw-004/slot-018MSSRO_based_VCRO: A high-performance, separately driven, noise-canceling, skew-based Voltage Controlled Ring Oscillator designed in the SKY130 Process.mpw-004/slot-019APPROXIMATE Multiplier: This project implements an approximate multiplier for image processing applications.mpw-004/slot-020ICD_FAST_NU_MPW4: This is MPW-4 submission by ICD Lab at FAST NU Islamabad. It contains LNA, Opamp, BGR, WPT module.mpw-004/slot-021RRAM_testchip: This submission is to test rram and its programming circuit using for eFPGA.mpw-004/slot-022REST: REST (resource efficient sram based tcam).mpw-004/slot-023ASIC Design of...: Space application Integrated Circuits (ICs) are prone to radiation particles, which are present in the form of electrons, protons, and heavy ions, generated from solar flares or space radiations.mpw-004/slot-024Sky130 RadTol Test Chip: Test structures for the study of ionizing radiation tolerance in the Skywater 130 process.mpw-004/slot-025Two Stage CMOS OPAMP: This project presents the design of a two stage CMOS Operational Amplifier.mpw-004/slot-026Karplus-Strong Guitar: Physically modeled guitar strings using the Karplus-Strong algorithm with some extensions by Jaffe & Smith.mpw-004/slot-027Karplus-Strong...: Two string version of Karplus-Strong Guitar.mpw-004/slot-028yifive_a2: RISC-V based sub system.mpw-004/slot-029Coriolis Test SoC - MPW4: Test SoC using Amaranth; Coriolis; PDKMaster for MPW4.mpw-004/slot-030SAR-ADC and...: This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clock generator.mpw-004/slot-031junga_soc_mpw4: Simple vexriscv based SoC.mpw-004/slot-032Ibtida-II: This submission is for Ibtida-I which was selected for the First MPW Shuttle.mpw-004/slot-033Azadi_II: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-I and few more this time, which were not stable at the time of Azadi-I.mpw-004/slot-034Ariel eFPGA: This is a part of Uranus FPGA project.mpw-004/slot-035Current Starved VCO: This project presents the design of a Current Starved Voltage Controlled Oscillator.mpw-004/slot-036Updown Counter (Test): A simple Updown counter for demo purpose.mpw-004/slot-037SkullFET: Barebone MOSFET transistors.mpw-004/slot-038CMOS...: A simple rail-to-rail comparator with its bias circuitry to test the SKY130 analog design flow.mpw-004/slot-039Kasirga K0: RISC-V SoC.mpw-004/slot-040IOTestVehicle: Test chip for higher speed IO pad cells.mpw-005/foundrympw-005/slot-001PLL-based...: Time-based capacitive sensor interface using highly-digital custom building blocks.mpw-005/slot-002mpw5_cache: We have integrated a smaller version of the 4-way set associative 256B L1 cache as user project area in caravel SoC.mpw-005/slot-003Zero to ASIC...: Zero to ASIC course group submission MPW5.mpw-005/slot-004Zero to ASIC...: Zero to ASIC MPW2 rerun on MPW5.mpw-005/slot-005Zero to ASIC...: Zero to ASIC MPW3 rerun on MPW5.mpw-005/slot-006Zero to ASIC...: Zero to ASIC MPW4 rerun on MPW5.mpw-005/slot-007ActuatorController: A phased PWM controller for micro motor control.mpw-005/slot-008Microwatt MPW5: Microwatt is a 64 bit OpenPOWER core written in VHDL.mpw-005/slot-009armleo_gpio_mpw5: armleo_gpio is a input output IP that is designed to handle 12pF @ 100MHz.mpw-005/slot-010FABulous_eFPGA: Demonstration of the open FABulous eFPGA using the OpenLane flow.mpw-005/slot-011I2C Controller: I2C bus controller transmits 8-bit serial data to multiple targets.mpw-005/slot-012LBIST-MBIST: Logic BIST with Scan Chain to detect struck at fault MBIST with 4 Location Row Redundancy Support.mpw-005/slot-013Riscduino-DCore: Riscduino with Dual RISC V 32bit core.mpw-005/slot-014Riscduino-QCore: Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.mpw-005/slot-015high_speed_vco: 3GHz High Speed VCO.mpw-005/slot-016OpenFASOC-cryo-gen: Automated Test scribes for cryogenic PDK generation and SPICE models enhancements using OpenFASOC Project done in collaboration with NIST.mpw-005/slot-017Microwave Signal...: 2.87 GHz microwave signal generator with a small programmable sweep step size.mpw-005/slot-018PICO Design...: This project includes two different designs submitted as part of SSCS PICO-2021.mpw-005/slot-019ASK Modulator...: This design contains an ASK Modulator that outputs signals in the 2.mpw-005/slot-020Baseband...: An Automatic Gain Control (AGC) feedback-loop oriented towards baseband applications (0-600 MHz) without the need for integrated inductors.mpw-005/slot-021Azadi_III: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II.mpw-005/slot-022TIA for physic...: This project implements a low-noise high bandwidth (~1GHz) transimpedance amplifier (TIA).mpw-005/slot-023qf105: Lanai-based microcontroller, implemented in Bluespec.mpw-005/slot-024Coriolis Test...: VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be theoretically linux-capable.mpw-005/slot-025junga_soc_mpw5: Simple vexriscv based SoC.mpw-005/slot-026NAND Flash MPW-5: Small hand-drawn NAND flash array.mpw-005/slot-027kasirga-c0-mpw-5: RISC-V SoC.mpw-005/slot-028Delta-Sigma...: As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC, with a maximized digital and minimized analog content.mpw-005/slot-029WirelessEnergyHarvesting: Improving WEH systems through voltage boosting and component sharing.mpw-005/slot-030Raster_engine: An implementation of rasterization engine using Skywater 130 nm PDK.mpw-005/slot-031DDR3 SSTL Test: Test chip for a DDR3 SSTL driver.mpw-005/slot-032PSRAM Interface with PRNG: HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.mpw-005/slot-033ALU: Digital design that compares the ALU results.mpw-005/slot-0344ft4: an MCS-4 clone (4004, 4001, 4002).mpw-005/slot-035RNG CHAOS: In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.mpw-005/slot-036UETRV-ECore: UETRV-ECore: An embedded class RISC V based Motor Control SoC.mpw-005/slot-037Systolic_array: We design a 2-D systolic array architecture as shown in teh figure.mpw-005/slot-038ReRAM Test: Testing ReRAM structures.mpw-005/slot-039Pseudo-Secure Memory: SRAM based pseudo-secure memory.mpw-005/slot-040Asynchronous...: Asynchronous Fibonacci counter using two phase dual rail logic.mpw-006/foundrympw-006/slot-001Free and open...: Hardware accelerator that implements standard encryption algorithm AES ECB.mpw-006/slot-002Microwatt MPW6: Microwatt is a 64 bit OpenPOWER core written in VHDL.mpw-006/slot-003Hack SoC - MPW-6: Hardware implementation of the Hack Computer from the Nand to Tetris courses.mpw-006/slot-004Riscduino-DCore(D3): Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.mpw-006/slot-005Riscduino-QCore(Q2): Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.mpw-006/slot-006Riscduino-SCore(S4): Arduino pin compatible Single RISCV 32 Bit core Project.mpw-006/slot-007SonaronChip8: process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz (low ultrasonic band).mpw-006/slot-008FT8 Receiver Test: A sample tapeout to test needed circuitry for a fully-functional FT8 transceiver.mpw-006/slot-009Azadi_DFT: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II.mpw-006/slot-010SRAMTestVehicleSequel: Iteration on SRAM test vehicle that was not selected for MPW5.mpw-006/slot-011ISA 16 bit Microprocessor: This is simple microprocessor.mpw-006/slot-012Asicle rollover: Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.).mpw-006/slot-01310b ADC and...: This submission features: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network.mpw-006/slot-014YONGA-Modbus Controller: A Modbus controller which has a read(03h) and a write(10h) function.mpw-006/slot-015ChristmasTreeCont...: Christmas tree controller (MPW5 ReRun).mpw-006/slot-016OpenRAM Test Design: This project was designed to be able to test the SRAM macros generated using OpenRAM flow.mpw-006/slot-0174 x PWM: PWM (Pulse Width Modulation) modules (resubmission from MPW-5).mpw-006/slot-018HyperRAM Interface: Resubmission of Steve Goldsmith's project.mpw-006/slot-019Adaptive...: We make implementation of a flexible 32-point Discrete Cosine Transform (DCT).mpw-006/slot-020CMOS cascode...: This is a high speed dynamic comparator.mpw-006/slot-021CMOS High Speed...: This is a novel dynamic comparator design that improves the common mode performance.mpw-006/slot-022ORDER_PRGA_MPW6: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBsmpw-006/slot-023Temporal Runtime...: This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of temporal logic formulas.mpw-006/slot-024MARMOT RISC-V SOC: Targeting 5-year continuous operation, a solar panel, a power supply board, a logic board, and lithium batteries are to be integrated in a waterproof housing to form an IoT.mpw-006/slot-025RNG MULTI SCROLL CHAOS: In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.mpw-006/slot-026Mixed_signal_circ...: Basic ReRAM, Floating Gate, and other analog structures.mpw-006/slot-027Mixed_signal_circuits_v2: Mixed signal circuits for analog synapses.mpw-006/slot-028direct...: This project contains blocks of a receiver.mpw-006/slot-029Floating_Point_Un...: This is the Floating point unit which supports the IEEE-754 Half Precision format.mpw-006/slot-030Floating_Point_Un...: This is the first ever Bfloat16 precision floating point unit designed by undergraduate students of DHA Suffa University Pakistan.mpw-006/slot-031Floating_Point_Un...: This is the first ever Single Precision Floating Point Unit designed by Undergraduate Students of DHA Suffa Univeristy.mpw-006/slot-032Experiar SoC: Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.mpw-006/slot-033my_caravel_analog_project: This is my first project. 6-bit saradc.mpw-006/slot-034Efabless_MPW6_riscduino: This is a clone project from dineshannayya/riscduino.mpw-006/slot-035Motius Pong: The first game: PONG.mpw-006/slot-036SoC_Now: This SoC is generated by the SoC Now Generator which is the final year project of undergraduate students.mpw-006/slot-037ORDER_PRGA_MPW6_v2: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBsmpw-006/slot-038Optimised Strong...: This is the design of an optimised Strong ARM Latch using modified particle swarm optimisation.mpw-006/slot-039riscduino_qcore_folk: folk of riscduino_qcore for test.mpw-006/slot-040Tensor...: Using NNgen to generate circuits.mpw-007/foundrympw-007/slot-001TinyTapeout: Test to put 500 100x100um designs onto one chip. More info at to ASIC...: Zero to ASIC course group submission MPW7.mpw-007/slot-003Microwatt MPW7: Microwatt is a 64 bit OpenPOWER core written in VHDL.mpw-007/slot-004YONGA-CAN Controller: YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.mpw-007/slot-005RocketAlpha: This project demonstrates a customized Rocket Chip SoC, generated from Chipyard.mpw-007/slot-006Riscduino-DCore(D3): Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.mpw-007/slot-007Riscduino-QCore(Q2): Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.mpw-007/slot-008Riscduino-SCore(S4): Arduino pin compatible Single RISCV 32 Bit core Project.mpw-007/slot-009Nanofabrication...: Test Structures for NIST's Nanofabrication Project.mpw-007/slot-010SRAMTestVehicleG3: Iteration on SRAM test vehicle that failed to be selected for MPW5 and MPW6.mpw-007/slot-011Analog Frontend...: This is a simple analog fronted for particle detection.mpw-007/slot-012ISA 16-bit Microprocessor: This is simple microprocessor.mpw-007/slot-013ReRAM crossbar: ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication.mpw-007/slot-014Trainable NN: Neural network with on-chip training.mpw-007/slot-01510b ADC and...: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network.mpw-007/slot-016Bitcoin Mining Asic: This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.mpw-007/slot-017YONGA-MCU: Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C.mpw-007/slot-018SoomRV: SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor.mpw-007/slot-019Marmot RISC-V...: Increased features (plus 8KB D-Cache and 3ch PWM)and improved clocking (25MHz > 50MHz) by mastering tools since MPW-6 MARMOT RISC-V, three months ago.mpw-007/slot-020Mixed_signal_circ...: We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog circuits for mixed-signal computing.mpw-007/slot-021FPGA_Programming_...: User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and AES/SHA cores.mpw-007/slot-022WARP-V: WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I.mpw-007/slot-023Leaf (mpw7): Leaf is a small 32-bit RISC core for simple applications.mpw-007/slot-024In memory computing SRAM: SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.mpw-007/slot-025RNG based on a...: A random number generator that uses the chaotic signals from a figaro based ring oscillator to generate bits.mpw-007/slot-026ReRAM-Controller-MPW7_v2: This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.mpw-007/slot-027Enhanced Chaotic...: Two general frameworks called NLCS and FPCS are developed for building robust chaotic system based on existing seed maps.mpw-007/slot-028In memory computing RRAM: The project includes RRAM In Memory Computing Accelerator, by researchers mentioned below under the supervision of Prof: Manan Suri (NVM & Neuromorphic Hardware Research Group IIT-Delhi, https://web.mpw-007/slot-029mpw-007/slot-030TopmetalSe-DPS: The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the Selena Neutrino experiment as an imager for rare nuclear processes in amorphous Selenium.mpw-007/slot-031Chaos Automaton: An array of 'Chaos Cells' that pass data onto one another in a loop, allowing for modifications to the data based on inputs, while the entire snake of data can be read at once.mpw-007/slot-032mpw-007/slot-033Waveform Generator: A generic waveform generator divided into stimulus and driver units that can be arbitrarily interconnected.mpw-007/slot-034Rift2Core: Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.mpw-007/slot-035Rift2Go_2300: This is a real Rift2Core CPU now, I remove L2-cache, and implement the L1-ICache L1-Dcache with Flip-flop.mpw-007/slot-036mpw-007/slot-037Systolic Array...: Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs.mpw-007/slot-038crypto_aes128: AES128 project test.mpw-007/slot-039Graphics Controller: The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.mpw-007/slot-040PRGA-test: An initial attempt to create a Test chip.mpw-008/foundrympw-008/slot-001mpw-008/slot-002mpw-008/slot-003mpw-008/slot-004mpw-008/slot-005mpw-008/slot-006mpw-008/slot-007mpw-008/slot-008mpw-008/slot-009mpw-008/slot-010mpw-008/slot-011mpw-008/slot-012mpw-008/slot-013mpw-008/slot-014mpw-008/slot-015mpw-008/slot-016mpw-008/slot-017mpw-008/slot-018mpw-008/slot-019mpw-008/slot-020mpw-008/slot-021mpw-008/slot-022mpw-008/slot-023mpw-008/slot-024mpw-008/slot-025mpw-008/slot-026mpw-008/slot-027mpw-008/slot-028mpw-008/slot-029mpw-008/slot-030mpw-008/slot-031mpw-008/slot-032mpw-008/slot-033mpw-008/slot-034mpw-008/slot-035mpw-008/slot-036mpw-008/slot-037mpw-008/slot-038mpw-008/slot-039mpw-008/slot-040