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Skywaters 130nm LDO Design Integrated in Caravel

License CI Caravan Build

This is a caravel that has an LDO Design implemented on Skywaters 130nm technology.We have 2 versions of our LDO. The difference between the 2 versions lies in the bandgap compensation capacitor and the startup circuit.

Circuit Design

The implementation of the LDO version 1 is as follows: The pins are integrated in caravel as follows: Enable pin is connected to io_in_3v3[14]. GND pin is connected to io_analog[7] VDD pin is connected to io_analog[6]. ldo_out pin is connected to io_analog[5].

Schematic

Image of LDO schematic

Error Amplifier

Image of LDO_Error amplifier

Bandgap

Image of LDO_BGR

LDO Simulation

We have an enable switch so all the following analysis when the enable signal is high.

a. DC analysis

We used dc analysis for displaying the operating point for proper biasing of transistors and also dc sweep of output voltage against variations in supply and temperature to calculate dropout voltage,line regulation,temperature coefficient.

Supply variation

We made dc sweep on the supply and plotted voltage of the output node and vdd node overlaid on the same plot @Load current = 0.1mA Image of LDO_Vout_vs_Vin

@Load current = 10mA Image of LDO_Vout_vs_Vin

@Load current = 100mA Image of LDO_Vout_vs_Vin

Temperature variation

We made dc sweep on temperature from 0 to 85°C and plotted the output voltage vs temperature from which we found temperature coeffiecient in ppm/°C. @Load current = 100uA Image of LDO_Vout_vs_Vin

@Load current = 10mA Image of LDO_Vout_vs_Vin

c. AC analysis

PSRR

We used AC analysis by injecting small ac signal over the supply and plotted the output voltage in dB which refers to the PSRR vs Frequency.

Image of LDO_PSRR

Stability analysis

We made the above testbench to cut the feedback loop of the ldo and inject ac signal and then measure the loop gain and phase to find phase margin.

d. Transient analysis

Line Transient

We used transient analysis to show the line transient by varying the supply from 0 to vdd where the nominal supply voltage is 2.3v. When VDD varies from 0 to 2.3v Image of LDO_Transient When VDD varies from 2 to 3v Image of LDO_Transient

Load Transient

The load is varied from 0.1mA to 10mA where the load is modeled as current source varied as PWL source where the output voltage suffers from under shoot of 40mV due to change of load current from 0.1mA to 10mA in 10uS then it settles back to its original value so we used this analysis to measure the load regulation.

The plot includes load current variation and ac-coupled ldo_output overlaid on the same plot. Image of LDO_netlist

Turn-on Characteristic

We have an enable signal so we varied it from 0 to Vin in 0.1uS and plotted the ldo_out. The start up time is less than 10uS. Image of LDO_netlist

e. Testbench netlist

Image of LDO_netlist

Simulation results

The typical conditions are tt corner ,load of 50uA, T=27°C , VDD=2.3V , We have a script to automate running process corners then getting their statistical distribution where the variation of the load from 50uA till 100mA is included in the corners

SpecificationTT
Temperature Coeffiecient49.4 ppm/°C
Dropout Voltage @IL=0.1mA0.211mV
Dropout Voltage @IL=10mA85.6mV @IL=10mA
Dropout Voltage @IL=100mA168.45mV @IL=100mA
Line Regulation0.0325 mv/v
Load Regulation0.06mV IL=0.1mA till IL=10mA
PSRR @ 100Hz88.1dB
PSRR @ 100kHz44.7dB
Load range50uA -> 100mA
Phase Margin50.1°
Quiescent Current130uA
Startup time7uS

Layout Design

Image of layout_version_1

Analog User Project Documentation

Running LVS command:

python3 scripts/run_standard_lvs.py gds/ldo_v1/ldo_flattened_f.gds.gz extracted.spi xschem/ldo_v1/ldo_v1_lvs.spice report.lvs ldo_flattened_f

Refer to README for this sample project documentation.

The implementation of the LDO version 2 is as follows:

The pins are integrated in caravel as follows: Enable pin is connected to io_in_3v3[12]. GND pin is connected to io_analog[0] VDD pin is connected to io_analog[4]. ldo_out pin is connected to io_analog[2,3]: we used two available thin pads connected to each other to be able to carry high currents.

Schematic

Image of LDO schematic

Error Amplifier

Image of LDO_Error amplifier

Bandgap

Image of LDO_BGR

LDO Simulation

We have an enable switch so all the following analysis when the enable signal is high.

a. DC analysis

We used dc analysis for displaying the operating point for proper biasing of transistors and also dc sweep of output voltage against variations in supply and temprature to calculate dropout voltage,line regulation,temperature coefficient.

Supply variation

We made dc sweep on the supply and plotted voltage of the output node and vdd node overlaid on the same plot @Load current = 0.1mA Image of LDO_Vout_vs_Vin

@Load current = 10mA Image of LDO_Vout_vs_Vin

@Load current = 100mA Image of LDO_Vout_vs_Vin

Temperature variation

We made dc sweep on temperature from 0 to 85°C and plotted the output voltage vs temperature from which we found temperature coeffiecient in ppm/°C. @Load current = 100uA Image of LDO_Vout_vs_Vin

@Load current = 10mA Image of LDO_Vout_vs_Vin

c. AC analysis

PSRR

We used AC analysis by injecting small ac signal over the supply and plotted the output voltage in dB which refers to the PSRR vs Frequency.

Image of LDO_PSRR

Stability analysis

We made the above testbench to cut the feedback loop of the ldo and inject ac signal and then measure the loop gain and phase to find phase margin.

d. Transient analysis

Line Transient

We used transient analysis to show the line transient by varying the supply from 0 to vdd where the nominal supply voltage is 2.3v. When VDD varies from 0 to 2.3v Image of LDO_Transient When VDD varies from 2 to 3v Image of LDO_Transient

Load Transient

The load is varied from 0.1mA to 10mA where the load is modeled as current source varied as PWL source where the output voltage suffers from under shoot of 40mV due to change of load current from 0.1mA to 10mA in 10uS then it settles back to its original value so we used this analysis to measure the load regulation.

The plot includes load current variation and ac-coupled ldo_output overlaid on the same plot. Image of LDO_netlist

Turn-on Characteristic

We have an enable signal so we varied it from 0 to Vin in 0.1uS and plotted the ldo_out. The start up time is less than 10uS. Image of LDO_netlist

e. Testbench netlist

Image of LDO_netlist

Simulation results

The typical conditions are tt corner ,load of 50uA, T=27°C , VDD=2.3V , We have a script to automate running process corners then getting their statistical distribution where the variation of the load from 50uA till 100mA is included in the corners

SpecificationTT
Temperature Coeffiecient49.4 ppm/°C
Dropout Voltage @IL=0.1mA0.211mV
Dropout Voltage @IL=10mA85.6mV @IL=10mA
Dropout Voltage @IL=100mA168.45mV @IL=100mA
Line Regulation0.0325 mv/v
Load Regulation0.06mV IL=0.1mA till IL=10mA
PSRR @ 100Hz84.3dB
PSRR @ 100kHz27dB
Load range50uA -> 100mA
Phase Margin50.1°
Quiescent Current128uA
Startup time1.3uS

Layout Design

Image of layout_version_2

Analog User Project Documentation

Running LVS command:

python scripts/run_standard_lvs.py gds/ldo_v1/ldo_flattened_f.gds extracted.spi xschem/ldo_v1/ldo_v1_lvs.spice report.lvs ldo_flattened_f ldo_v1_lvs

Refer to README for this sample project documentation.