foundryslot-001StdCellLib: This is a testwafer project with standard cells that were automatically generated by the Libresilicon StdCellLib generator.slot-0021V8 LDO Design...: 1V8 LDO Design in Skywaters 130nm.slot-003slot-004Zero to ASIC...: MPW3 submission.slot-005Crypto Accelerator v2: SHA/AES accelerator and VGA graphics demo.slot-006picorF0: CAN bus controller and teaching-oriented CPU core.slot-007Randsack: Random number generators, PUFs, and resubmission of MPW-1 Softshell.slot-008YONGA-100M Ethernet: YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.slot-009Approximate Multiplier: This project is implementation of approximate multiplier published in ACM TODAES journal 2021, titled 'Energy Efficient Error Resilient Multiplier Using Low-power Compressors'.slot-010VSD SRAM: Aims at design of a SRAM cell array with a configuration of 1.slot-011Key Value store: Key value store implemented on asic.slot-012MBIST Controller: MBIST controller with Row Redundancy Support.slot-013Riscduino: Arduino compatible Risc-V Based SOC.slot-014caravel_periphera...: A attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO , WS281B led controller to the Caravel SoC via the wishbone bus.slot-015UCSC OpenRAM Test Chip v2: This project contains a test chip for several OpenRAM memory configurations.slot-016Class-D Audio Amplifier: This project is intended to implement a closed-loop class-d audio amplifier with 1.slot-017Efabless processor: Basic design to familiarize with this service.slot-018ToolTest gpioCtrl: Digital test design with simple GPIO control for toolchain testing.slot-019Comparator and...: 3v3 comparator with 1v8 output.slot-020Current Starved...: This project focuses on design of a Current Starved VCO using Google Skywater (sky130) Technology node with operating voltage of 1.slot-021Two Stage CMOS...: Two Stage CMOS Operational Amplifier.slot-022Sziklai Pair Amplifier: This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130) Technology node with operating voltage of 1.slot-023Two Stage CMOS...: CMOS OPAMP is Basic building block of analog and Mixed signal circuits.slot-024Pre-Trained...: This project implements a pre-trained neural network for hand-written digits from MNIST dataset.slot-025ROTFPGA: A reconfigurable logic circuit made of identical rotatable tiles.slot-026TreePRAM: Implements a version of the parallel random-access machine used in theoretical computer science courses with a memory sharing model based on a binary tree of processor cores.slot-027TreePRAM-red: Reduced version of TreePRAM for faster builds and tests. Not submitting for the shuttle.slot-028caravel_jacaranda-8: PicoRV & Jacaranda-8 - It's a hobby heterogeneous processor!.slot-029Sudoku Accelerator: Sudoku accelerator module that is capable of running an 'only candidate' pass in 23 cycles and a 'naked singles' pass in 108 cycles.slot-030Fixed2Float_Converter: This project is implementation for conversion of 19bit fixed point number to single precision IEEE floating point number.slot-031High Speed Adder: This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.slot-032My_Proj: Nahh.slot-033PWM_Test: nahhhh.slot-034Elpis Light processor: This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle in-order processor based on RISC-V architecture, mixed with some MIPS ideas.slot-035VSDBabySoC: VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.slot-036VSDMemSoC: VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM Instruction Memory (IMem) to separate the processor core and the IMem.slot-037Caravel SRAM Test: The project instantiates an SRAM block in the user project area for testing.slot-0388-bit SAR-ADC...: This is a Analog to Digital Converter based on the popular SAR architecture.slot-039Caravel HyperRAM...: Project instantiates HyperRAM driver for external memory chip (8MB version) and additional OpenRAM 1kB block (32x256B).slot-040Caravel: A template SoC for Google sponsored Open MPW shuttles for SKY130.