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  1. 9715af4 final gds oasis by Jeff DiCorpo · 1 year, 1 month ago main
  2. 77f1423 Auto updated submodule references by Git bot · 1 year, 1 month ago
  3. 85978e7 Auto updated submodule references by Git bot · 1 year, 3 months ago
  4. 4a53bf1 Updated code for 1 block SRAM, attempted to add a 32x512 block, but failed due to DRC errors (couldn't resolve). by Michael Tomlinson · 1 year, 3 months ago
  5. 1cf6a75 Single SRAM test chip. by Michael Tomlinson · 1 year, 3 months ago

Caravel User Project

License UPRJ_CI Caravel Build

This is a simple project connecting a 256x32 SRAM block to the wishbone interface for testing. The SRAM block is directly connected to the wishbone bus at address 0x3000000. An additional perpherial was made to write to the io ports when address 0x30008000 is written to.

Refer to README for this sample project documentation.