| commit | 4a53bf1bfdc8811373f80b5448b71e7af7f0bd58 | [log] [tgz] |
|---|---|---|
| author | Michael Tomlinson <mtomlin5@jh.edu> | Fri Nov 12 09:14:56 2021 -0500 |
| committer | Michael Tomlinson <mtomlin5@jh.edu> | Fri Nov 12 09:14:56 2021 -0500 |
| tree | 64ff10f2a2091d081c1fb18b60b26ed9fdb017b4 | |
| parent | 1cf6a75b5d8ae6db915fcbc4a36c0a22f70cc2a3 [diff] |
Updated code for 1 block SRAM, attempted to add a 32x512 block, but failed due to DRC errors (couldn't resolve).
This is a simple project connecting a 256x32 SRAM block to the wishbone interface for testing. The SRAM block is directly connected to the wishbone bus at address 0x3000000. An additional perpherial was made to write to the io ports when address 0x30008000 is written to.
Refer to README for this sample project documentation.