commit	1cf6a75b5d8ae6db915fcbc4a36c0a22f70cc2a3	[log] [tgz]
author	Michael Tomlinson <mtomlin5@jh.edu>	Thu Nov 11 18:08:07 2021 -0500
committer	Michael Tomlinson <mtomlin5@jh.edu>	Thu Nov 11 18:08:07 2021 -0500
tree	7bcf05bb8706f5d37f74ccae938cfcfbb2b4a7c6
parent	dfc479e2bde9546bf63da55866c9fe3959bdc79f [diff]

Single SRAM test chip.

.gitignore[diff]
README.md[diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_proj_example/macro.cfg[Added - diff]
openlane/user_proj_example/pin_order.cfg[diff]
openlane/user_proj_example/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib[Added - diff]
openlane/user_proj_example/unmod/config.json[Renamed from openlane/user_proj_example/config.json - diff]
openlane/user_proj_example/unmod/config.tcl[Added - diff]
openlane/user_proj_example/unmod/pin_order.cfg[Added - diff]
openlane/user_proj_example/user_proj_example.sdc[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/old/config (copy).tcl[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/memtest_test/Makefile[Renamed from verilog/dv/mprj_stimulus/Makefile - diff]
verilog/dv/memtest_test/memtest_test.c[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.00.split[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.01.split[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.02.split[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.03.split[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.04.split[Added - diff]
verilog/dv/memtest_test/memtest_test.vcd.gz.05.split[Added - diff]
verilog/dv/memtest_test/memtest_test_tb.v[Renamed from verilog/dv/io_ports/io_ports_tb.v - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/dpram_gen.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/functional_stim.sp[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/run_drc.sh[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/run_ext.sh[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/run_lvs.sh[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/setup.tcl[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.html[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.lef[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.log[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.lvs.sp[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.py[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.sp[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/functional_stim.sp[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/run_drc.sh[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/run_ext.sh[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/run_lvs.sh[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/setup.tcl[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.html[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.lef[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.log[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.lvs.sp[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.py[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.sp[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib[Added - diff]
verilog/rtl/unmodified/uprj_netlists.v[Added - diff]
verilog/rtl/unmodified/user_proj_example.v[Added - diff]
verilog/rtl/unmodified/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

93 files changed

tree: 7bcf05bb8706f5d37f74ccae938cfcfbb2b4a7c6

README.md

Caravel User Project

This is a simple project connecting a 256x32 SRAM block to the wishbone interface for testing. The SRAM block is directly connected to the wishbone bus at address 0x3000000. An additional perpherial was made to write to the io ports when address 0x30008000 is written to.

Refer to README for this sample project documentation.