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Branches

  1. 2cf5cb0 final gds oasis by Jeff DiCorpo · 1 year, 1 month ago main
  2. a5ea8a3 Updated submodule wb_hyperram to newest version. by embelon · 1 year, 2 months ago
  3. 9e314b9 Fixed unaligned access over Wishbone bus that results in picorv32 hang. Improved readability. by embelon · 1 year, 2 months ago
  4. af9dbfc Changed interval and max time for completing dv. by embelon · 1 year, 2 months ago
  5. 18d883a Updated clock generation for testbench. by embelon · 1 year, 3 months ago

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory blockSpaceAddressSize
HyperRAM ext. chipRAM0x3000_0000 - 0x307f_ffff8MB
HyperRAM ext. chipRegisters0x3080_0000 - 0x3080_ffffmax 64k registers, 16bit each
HyperRAM driverCSRs0x3081_0000 - 0x3081_ffffmax 64kB, 16k CSRs
OpenRAMRAM0x30c0_0000 - 0x30c0_ffffmax 64kB