Fixed unaligned access over Wishbone bus that results in picorv32 hang. Improved readability.
1 file changed
tree: 441fdcb8ceefca9b562cb6bc8aa96a7f269ced70
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  15. Makefile

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Additional memory (internal 1kB of OpenRAM and HyperRAM driver for external memory chip) connected through Wishbone to Caravel SoC for MPW submission

Memory blockSpaceAddressSize
HyperRAM ext. chipRAM0x3000_0000 - 0x307f_ffff8MB
HyperRAM ext. chipRegisters0x3080_0000 - 0x3080_ffffmax 64k registers, 16bit each
HyperRAM driverCSRs0x3081_0000 - 0x3081_ffffmax 64kB, 16k CSRs
OpenRAMRAM0x30c0_0000 - 0x30c0_ffffmax 64kB