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High Speed Adder

This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.

I/Os

Inputs: in1, in2 each of 18 bits
        Mode for add/sub selection
Output: Sum which is of 19 bits.

Block Diagram

Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit. acc_cla

EDA Tools and Environment

Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness

Pre-Synthesis Simulation

Post-Synthesis Simulation

Screenshot (461)

RTL to GDSII

layout