| commit | 4b9c68788044aebff886e598967225c4dc3cca75 | [log] [tgz] |
|---|---|---|
| author | Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com> | Wed Oct 20 23:31:05 2021 +0530 |
| committer | GitHub <noreply@github.com> | Wed Oct 20 23:31:05 2021 +0530 |
| tree | a1b5b58132c92a766c599f88b47f1aecff62544f | |
| parent | aa0cb00d81d0c83e9b84ca05eac4ef0d2e2e47c7 [diff] |
Update README.md
This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.
Inputs: in1, in2 each of 18 bits
Mode for add/sub selection
Output: Sum which is of 19 bits.
Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit. 
Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness
