| commit | e16a3f214aee66b37fa6fd3461730d71df0a8db7 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 29 03:27:40 2021 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 29 03:27:40 2021 -0800 |
| tree | f0461caa288a938683a2fd27eba0c61087a77c1f | |
| parent | 76fb2277b4582afb521d9aa993cfe550b9d5ba37 [diff] |
final gds oasis
This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.
Inputs: in1, in2 each of 18 bits
Mode for add/sub selection
Output: Sum which is of 19 bits.
Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit. 
Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness
