Update README.md
1 file changed
tree: afdb1c1548da3e14d3a9d7f7637eeec3a7243a96
  1. caravel/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. precheck_results/
  9. signoff/
  10. Simulations/
  11. spi/
  12. verilog/
  13. info.yaml
  14. LICENSE
  15. Makefile
  16. README.md
  17. README.md.bak
README.md

High Speed Adder

This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.

I/Os

Inputs: in1, in2 each of 18 bits
        Mode for add/sub selection
Output: Sum which is of 19 bits.

Block Diagram

Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit. acc_cla

EDA Tools and Environment

Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness

Pre-Synthesis Simulation

Post-Synthesis Simulation

Screenshot (461)

RTL to GDSII

layout