| commit | 76fb2277b4582afb521d9aa993cfe550b9d5ba37 | [log] [tgz] |
|---|---|---|
| author | Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com> | Thu Oct 28 20:54:20 2021 +0530 |
| committer | GitHub <noreply@github.com> | Thu Oct 28 20:54:20 2021 +0530 |
| tree | afdb1c1548da3e14d3a9d7f7637eeec3a7243a96 | |
| parent | 4b9c68788044aebff886e598967225c4dc3cca75 [diff] |
Update README.md
This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.
Inputs: in1, in2 each of 18 bits
Mode for add/sub selection
Output: Sum which is of 19 bits.
Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit. 
Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness
