|author||Jeff DiCorpo <email@example.com>||Wed Dec 29 03:27:40 2021 -0800|
|committer||Jeff DiCorpo <firstname.lastname@example.org>||Wed Dec 29 03:27:40 2021 -0800|
final gds oasis
This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.
Inputs: in1, in2 each of 18 bits Mode for add/sub selection Output: Sum which is of 19 bits.
Step1: Precomputation of carry status signals of “Generate”, “Propagate”, “Kill”. Step2: Computation of actuaal carry signals for all bits. Step3: Final Sum computation by XORing Carry and propgate signals at each bit.
Process Node: Sky130nm Simulations:iverilog RTL to GDSII: Openlane SoC Wrapper: Caravel Harness