| /root/high_speed_adder/README.md.bak |
| /root/high_speed_adder/Makefile |
| /root/high_speed_adder/docs/environment.yml |
| /root/high_speed_adder/docs/Makefile |
| /root/high_speed_adder/docs/source/index.rst |
| /root/high_speed_adder/docs/source/conf.py |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/magic_drc_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_offgrid_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_pin_label_purposes_overlapping_drawing_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/tools.info |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_beol_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/xor_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_zeroarea_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_met_min_ca_density_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/gds.info |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/klayout_feol_check.total |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/logs/pdks.info |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/outputs/defines.v |
| /root/high_speed_adder/precheck_results/18_OCT_2021___15_19_27/outputs/reports/magic_drc_check.drc.report |
| /root/high_speed_adder/verilog/dv/Makefile |
| /root/high_speed_adder/verilog/dv/la_test2/la_test2_tb.v |
| /root/high_speed_adder/verilog/dv/la_test2/la_test2.c |
| /root/high_speed_adder/verilog/dv/la_test2/Makefile |
| /root/high_speed_adder/verilog/dv/la_test1/la_test1.c |
| /root/high_speed_adder/verilog/dv/la_test1/Makefile |
| /root/high_speed_adder/verilog/dv/la_test1/la_test1_tb.v |
| /root/high_speed_adder/verilog/dv/io_ports/Makefile |
| /root/high_speed_adder/verilog/dv/io_ports/io_ports_tb.v |
| /root/high_speed_adder/verilog/dv/io_ports/io_ports.c |
| /root/high_speed_adder/verilog/dv/mprj_stimulus/Makefile |
| /root/high_speed_adder/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/high_speed_adder/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/high_speed_adder/verilog/dv/wb_port/wb_port_tb.v |
| /root/high_speed_adder/verilog/dv/wb_port/Makefile |
| /root/high_speed_adder/verilog/dv/wb_port/wb_port.c |
| /root/high_speed_adder/verilog/rtl/uprj_netlists.v |
| /root/high_speed_adder/verilog/rtl/user_proj_example.v |
| /root/high_speed_adder/verilog/rtl/user_project_wrapper.v |
| /root/high_speed_adder/verilog/rtl/bakup/user_proj_example.v |
| /root/high_speed_adder/verilog/rtl/bakup/user_project_wrapper.v |
| /root/high_speed_adder/Simulations/pre_synthesis/adder.v |
| /root/high_speed_adder/Simulations/pre_synthesis/adder_tb.v |
| /root/high_speed_adder/Simulations/post_synthesis/adder.synthesis.v |
| /root/high_speed_adder/Simulations/post_synthesis/sky130_fd_sc_hd.v |
| /root/high_speed_adder/Simulations/post_synthesis/primitives.v |
| /root/high_speed_adder/Simulations/post_synthesis/gls.v |