ReRAM-Controller-MPW7_v2: This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.

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  1. 1bde9a7 final gds oasis by Jeff DiCorpo · 1 year, 3 months ago main
  2. 91c8bac added user_defines.v by Po-Chun Huang · 1 year, 3 months ago
  3. b201010 m5 by Po-Chun Huang · 1 year, 6 months ago
  4. 4c50f3b added spice and gds files by Po-Chun Huang · 1 year, 8 months ago
  5. d325e22 added ReRAM cells by Po-Chun Huang · 1 year, 8 months ago

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This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.


Refer to README for this sample project documentation. ~