| commit | d325e22a118b2c9da74e86d93cd616c0f21b5215 | [log] [tgz] |
|---|---|---|
| author | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 08:59:33 2022 -0400 |
| committer | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 08:59:33 2022 -0400 |
| tree | bdb18e4eda5d489795113d2ae4c804eee509cca7 | |
| parent | abd3f6f8640df088199b421a4ea714c17bb03411 [diff] |
added ReRAM cells
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.
Refer to README for this sample project documentation. ~