| commit | abd3f6f8640df088199b421a4ea714c17bb03411 | [log] [tgz] |
|---|---|---|
| author | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 08:40:03 2022 -0400 |
| committer | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 08:40:03 2022 -0400 |
| tree | c19746cafe1e15ff80f2ce63a0c431417094374a | |
| parent | 3efd3e2ed083bd3dafd91c6fd16fc43e2bcc94d6 [diff] |
Added 1T1R 256x256 module
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.
Refer to README for this sample project documentation. ~