| commit | b2010103bcafffddcf840761936436a5e10336e4 | [log] [tgz] |
|---|---|---|
| author | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Sat Sep 10 13:17:33 2022 -0400 |
| committer | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Sat Sep 10 13:17:33 2022 -0400 |
| tree | 8981dc1c0f86191ee9210083224ebe684c61f57a | |
| parent | 4c50f3b6716ceccbab24d16428c12cff6a987e9e [diff] |
m5
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.
Refer to README for this sample project documentation. ~