4T1R Testchip: RRAM testchip designed to evaluate 4t1r configuration.

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  1. 8579182 final gds oasis by Jeff DiCorpo · 1 year, 11 months ago main
  2. 0e88761 Updated readme by Ganesh Gore · 1 year, 11 months ago
  3. fedb7fd dummy changes to run precheck by Ganesh Gore · 2 years ago
  4. 9f52689 Updated GDS by Ganesh Gore · 2 years ago
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This repository contains test structure for RRAM based Multiplexers design. Please refere to following publications for detail.

[1] X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “Circuit Designs of High-performance and Low-power RRAM-based Multiplexers based on 4T(ransistor)1R(RAM) Programming Structure,” IEEE Transactions on Circuits and Systems - I, vol. 64, no. 5, pp. 1173-1186, May 2017. RANKED within the IEEE TCAS-I TOP POPULAR ARTICLES in May 2017. PDF

[2] X. Tang, G. De Micheli, P.-E. Gaillardon, “A High-performance FPGA Architecture Using One-Level RRAM-based Multiplexers,” IEEE Transactions on Emerging Topics in Computing (TETC), vol. 5, no. 2, pp. 210-222, April-June 2017. PDF