foundryslot-001Zero to ASIC...: Designs from the Zero to ASIC course.slot-002Zero to ASIC...: Re-hardened MPW2 group submission to fix clock issues and re-submit for MPW4.slot-003CMOS only...: Sub 1-V voltage supply, 3.slot-004pifive-soc: RISC-V SoC.slot-005RAM_Generator: This project is for the testing purpose.slot-006Space Controller: This design is a radiation tolerant UART server that can be used for low level control of multiple input/output ports during a radiation testing campaign.slot-007Randsack B1: Random number generators and PUFs.slot-0084T1R Testchip: RRAM testchip designed to evaluate 4t1r configuration.slot-009YONGA-Turbo Encoder: YONGA-Turbo Encoder is an implementation of a high-performance forward error correction (FEC) coding technique.slot-010ICESOC: Ibex Crypto eFPGA SoC.slot-011Key Value store 2: A key value store using a wishbone interface, developed using migen.slot-012Subservient-MPW4: An ASIC-adapted version of the award-winning bit-serial RISC-V processo SERV, resubmitted due to expected issues with mpw2.slot-013Logic BIST: Logic BIST with Scan Chain to detect struck at fault.slot-014riscduino-R1: A arduino pin compatible RISC V Project.slot-015slot-016slot-017CMOS Frequency...: 2.87 GHz frequency synthesizer with programmable sweep.slot-018MSSRO_based_VCRO: A high-performance, separately driven, noise-canceling, skew-based Voltage Controlled Ring Oscillator designed in the SKY130 Process.slot-019APPROXIMATE Multiplier: This project implements an approximate multiplier for image processing applications.slot-020ICD_FAST_NU_MPW4: This is MPW-4 submission by ICD Lab at FAST NU Islamabad. It contains LNA, Opamp, BGR, WPT module.slot-021RRAM_testchip: This submission is to test rram and its programming circuit using for eFPGA.slot-022REST: REST (resource efficient sram based tcam).slot-023ASIC Design of...: Space application Integrated Circuits (ICs) are prone to radiation particles, which are present in the form of electrons, protons, and heavy ions, generated from solar flares or space radiations.slot-024Sky130 RadTol Test Chip: Test structures for the study of ionizing radiation tolerance in the Skywater 130 process.slot-025Two Stage CMOS OPAMP: This project presents the design of a two stage CMOS Operational Amplifier.slot-026Karplus-Strong Guitar: Physically modeled guitar strings using the Karplus-Strong algorithm with some extensions by Jaffe & Smith.slot-027Karplus-Strong...: Two string version of Karplus-Strong Guitar.slot-028yifive_a2: RISC-V based sub system.slot-029Coriolis Test SoC - MPW4: Test SoC using Amaranth; Coriolis; PDKMaster for MPW4.slot-030SAR-ADC and...: This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clock generator.slot-031junga_soc_mpw4: Simple vexriscv based SoC.slot-032Ibtida-II: This submission is for Ibtida-I which was selected for the First MPW Shuttle.slot-033Azadi_II: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-I and few more this time, which were not stable at the time of Azadi-I.slot-034Ariel eFPGA: This is a part of Uranus FPGA project.slot-035Current Starved VCO: This project presents the design of a Current Starved Voltage Controlled Oscillator.slot-036Updown Counter (Test): A simple Updown counter for demo purpose.slot-037SkullFET: Barebone MOSFET transistors.slot-038CMOS...: A simple rail-to-rail comparator with its bias circuitry to test the SKY130 analog design flow.slot-039Kasirga K0: RISC-V SoC.slot-040IOTestVehicle: Test chip for higher speed IO pad cells.