Kasirga K0: RISC-V SoC.

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  1. 37c9d62 final gds oasis by Jeff DiCorpo · 2 years, 3 months ago main
  2. 772b7da Merge pull request #1 from olgunataberk/patch-1 by unrealismail · 2 years, 3 months ago
  3. de69c47 Update README.md by Ataberk Olgun · 2 years, 3 months ago
  4. 2d04601 update config.tcl by unrealismail · 2 years, 3 months ago
  5. 336a1cb Merge branch 'main' of github.com:kasirgalabs/kasirga-k0 into main by ataberk · 2 years, 3 months ago

Kasırga K0 RISC-V SoC

License UPRJ_CI Caravel Build

Table of contents


This repo contains the RISC-V based K0 SoC that utilizes caravel chip user space. K0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

K0 Block Diagram


Key Features




Running Full Chip Simulation


Hardening the Kasirga K0 using Openlane


Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck