commit	772b7da4ff5cb3dbcb5b440989930eeec4920b22	[log] [tgz]
author	unrealismail <iyuksel@etu.edu.tr>	Thu Dec 30 20:45:15 2021 +0300
committer	GitHub <noreply@github.com>	Thu Dec 30 20:45:15 2021 +0300
tree	5142abfb472e0fcf137bf643eceab03811768ec2
parent	2d0460170b26c5ac4084a6e94d0fd9d2fc31bcc5 [diff]
parent	de69c47ae9fe63e4c4f318945a173551a6f61c3c [diff]

tree: 5142abfb472e0fcf137bf643eceab03811768ec2

README.md

Kasırga K0 RISC-V SoC

Overview
K0 Block Diagram
Key Features
Prerequisites
Running Full Chip Simulation
Hardening the Kasirga K0 using Openlane
Checklist for Open-MPW Submission

Overview

This repo contains the RISC-V based K0 SoC that utilizes caravel chip user space. K0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

K0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga K0 using Openlane

TBA

Checklist for Open-MPW Submission

✔️ The project repo adheres to the same directory structure in this repo.
✔️ The project repo contain info.yaml at the project root.
✔️ Top level macro is named user_project_wrapper.
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
✔️ The hardened Macros are LVS and DRC clean
✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
✔️ XOR check passes with zero total difference.
✔️ Openlane summary reports are retained under ./signoff/
✔️ The design passes the mpw-precheck