commit	37c9d62556328a2a4c36e759785589c9bd29d19a	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Sun Jan 09 12:41:45 2022 -0800
committer	Jeff DiCorpo <jeffdi@efabless.com>	Sun Jan 09 12:41:45 2022 -0800
tree	14b81daac91a6740e71d4b89eea11bf73d009627
parent	772b7da4ff5cb3dbcb5b440989930eeec4920b22 [diff]

final gds oasis

92 files changed

tree: 14b81daac91a6740e71d4b89eea11bf73d009627

README.md

Kasırga K0 RISC-V SoC

Overview
K0 Block Diagram
Key Features
Prerequisites
Running Full Chip Simulation
Hardening the Kasirga K0 using Openlane
Checklist for Open-MPW Submission

Overview

This repo contains the RISC-V based K0 SoC that utilizes caravel chip user space. K0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

K0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga K0 using Openlane

TBA

Checklist for Open-MPW Submission

✔️ The project repo adheres to the same directory structure in this repo.
✔️ The project repo contain info.yaml at the project root.
✔️ Top level macro is named user_project_wrapper.
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
✔️ The hardened Macros are LVS and DRC clean
✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
✔️ XOR check passes with zero total difference.
✔️ Openlane summary reports are retained under ./signoff/
✔️ The design passes the mpw-precheck