blob: ac6c0f3c0f53748de6bec4701cbb44768dbefe8e [file] [log] [blame]
---
project:
description: "RISC-V SoC."
foundry: "SkyWater"
git_url: "https://github.com/kasirgalabs/kasirga-k0.git"
organization: "Kasirga Labs"
organization_url: "http://www.kasirgalabs.com/"
owner: "İsmail Emir Yüksel"
process: "SKY130"
project_name: "Kasirga K0"
project_id: "00000000"
tags:
- "in-order processor"
- "soc"
- "riscv"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "v1"
cover_image: "docs/source/_static/caravel_harness.png"