Clone this repo:

Branches

  1. 229830e final gds oasis by Jeff DiCorpo · 1 year, 1 month ago main
  2. a7302cc Update README.md by BYCakar · 1 year, 1 month ago
  3. eaeb0d9 Auto updated submodule references by Git bot · 1 year, 1 month ago
  4. 27613d3 Delete user_project_wrapper.gds by abdullahyildiz · 1 year, 1 month ago
  5. 428fa51 Delete user_proj_example.gds by abdullahyildiz · 1 year, 1 month ago

YONGA-Turbo Encoder

License UPRJ_CI Caravel Build

Table of contents

Overview

DVB-RCS2 Turbo Encoder

Turbo Encoder is used for FEC encoding for linear modulation.

Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)

First couple of parity bits (Y1W1) are generated from linearly ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.

The design involves two paths:

  1. Linear order path
  2. Interleaved path

Top-Level Diagram

alt text

-Input Data is stored at dual channel rams.

-AGU's (Address Generator Unit) generate data indices for linearly ordered and interleaved data inputs.

-Pre Encoder unit identifies initial state of the encoder.

-Encoder Core produces outputs according to the state and the inputs.

Synthesis Report

alt text

Implementation Report

alt text

-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1

Throughput

equation

‘N’ = input data block size in couple number ranging from 56 to 2396.

‘f’ = frequency in Mhz.

For 50 Mhz clock speed and N = 56, throughput equals to 31.5 Mbps.

For 50 Mhz clock speed and N = 2396, throughput equals to 33.3 Mbps.

Setup

To setup caravel, run the following

git clone https://github.com/yongatek/caravel_yonga-turbo-encoder.git
cd caravel_yonga-turbo-encoder
make install

Setup the pdk

export PDK_ROOT=<pdk-installation-path>
make pdk

Running Simulation

First, you will need to install the simulation environment, by

make simenv

Then set the environment properly

export PDK_ROOT=<pdk-installation-path>
export CARAVEL_ROOT=$(pwd)/caravel

Specify simulation mode

export SIM=RTL
# use the command below for GL simulation
# export SIM=GL

Run these commands to test YONGA-Turbo Encoder

# run Turbo Encoder WB test
make verify-turbo_encoder_wb_test
# run Turbo Encoder GPIO test
make verify-turbo_encoder_gpio_test

Hardening the User Project Macro using OpenLANE

First, you will need to install openlane to harden the user project macro

export OPENLANE_ROOT=<openlane-installation-path>
make openlane

To harden the user project macro run the following

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

List of Contributors

In alphabetical order:

  • Baris Bilgili
  • Burak Yakup Cakar
  • Muhammed Celik