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YONGA-Turbo Encoder

License UPRJ_CI Caravel Build

Table of contents


DVB-RCS2 Turbo Encoder

Turbo Encoder is used for FEC encoding for linear modulation.

Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)

First couple of parity bits (Y1W1) are generated from linearly ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.

The design involves two paths:

  1. Linear order path
  2. Interleaved path

Top-Level Diagram

alt text

-Input Data is stored at dual channel rams.

-AGU's (Address Generator Unit) generate data indices for linearly ordered and interleaved data inputs.

-Pre Encoder unit identifies initial state of the encoder.

-Encoder Core produces outputs according to the state and the inputs.

Synthesis Report

alt text

Implementation Report

alt text

-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1



‘N’ = input data block size in couple number ranging from 56 to 2396.

‘f’ = frequency in Mhz.

For 50 Mhz clock speed and N = 56, throughput equals to 31.5 Mbps.

For 50 Mhz clock speed and N = 2396, throughput equals to 33.3 Mbps.



Running Simulation


Hardening the User Project Macro using OpenLANE


List of Contributors

In alphabetical order:

  • Baris Bilgili
  • Burak Yakup Cakar
  • Muhammed Celik