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  1. 5c9b9ae final gds oasis by Jeff DiCorpo · 1 year, 1 month ago main
  2. b96fec9 Add GDS and GL Verilog by gatecat · 1 year, 1 month ago
  3. 4b231fc Auto updated submodule references by Git bot · 1 year, 1 month ago
  4. 19eb8ca Add info.yaml and top level gl verilog by gatecat · 1 year, 3 months ago
  5. b063f47 Add README by gatecat · 1 year, 3 months ago

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

  • Minerva RV32IM CPU
  • 512 bytes SRAM
  • (Q)SPI flash for code and data memory using spimemio from picosoc
  • HyperRAM for RAM extension using a derivative of litehyperbus
  • 8-bit GPIO
  • UART, timer, and interrupt controller

Built using: