Add GDS and GL Verilog

Signed-off-by: gatecat <gatecat@ds0.me>
2 files changed
tree: 00b36c07e7c49b57132750c83ca519a2d412d1e6
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. maglef/
  6. signoff/
  7. verilog/
  8. .gitignore
  9. .gitmodules
  10. info.yaml
  11. LICENSE
  12. Makefile
  13. README.md
README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

  • Minerva RV32IM CPU
  • 512 bytes SRAM
  • (Q)SPI flash for code and data memory using spimemio from picosoc
  • HyperRAM for RAM extension using a derivative of litehyperbus
  • 8-bit GPIO
  • UART, timer, and interrupt controller

Built using: