)]}'
{
  "commit": "b96fec9d2c6c26a517da8e8dba0ededfe741b6b7",
  "tree": "00b36c07e7c49b57132750c83ca519a2d412d1e6",
  "parents": [
    "4b231fc78b0df6e04c6f9872b57f4456ab464bfd"
  ],
  "author": {
    "name": "gatecat",
    "email": "gatecat@ds0.me",
    "time": "Tue Dec 21 21:18:10 2021 +0000"
  },
  "committer": {
    "name": "gatecat",
    "email": "gatecat@ds0.me",
    "time": "Wed Dec 29 15:43:19 2021 +0000"
  },
  "message": "Add GDS and GL Verilog\n\nSigned-off-by: gatecat \u003cgatecat@ds0.me\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e135b9e82bc317ff055e88bb7dc92d097c6e975b",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds.gz"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f881b92e5c390f83e0574561c6e07ca671afce6e",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_core_lambdasoc.v"
    }
  ]
}
