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Space Controller

License Caravel Build

Authors

  • Ivan Rodriguez-Ferrandez (UPC¹-BSC²)
  • Alvaro Jover-Alvarez (UPC¹-BSC²)
  • Leonidas Kosmidis (BSC²-UPC¹)
  • David Steenari (ESA³)
    ¹ Universitat Politècnica de Catalunya (UPC)
    ² Barcelona Supercomputing Center (BSC)
    ³ European Space Agency (ESA)

Main Version of the chip: 1.0V

Change Log

  • Version 1.0V:
    • TODO

Chip Layout

Description

This design is a radiation tolerant UART server that can be used for low level control of multiple input/output ports during a radiation testing campaign. The system features triple redundancy in order to ensure that the commands are properly executed.

In addition to simulation, the RTL design of the user project is verified also on a Xilinx Zybo Z7-20 FPGA using Vivado. The UART communication protocol is based on https://github.com/alexforencich/verilog-uart and its files are covered with the same open source license as the rest of the project (MIT).

How To Use The Chip

This chip uses the UART port for main communication. This communication port is used to send instructions and receive the requested output. The input is a 52 bit word for communication. In order to fill up the word, the values are sent one by one via the UART port. The 52 bit are divided in this well defined sections:

  • [51:49] 3 bit operation code.
  • [48:44] 5 bit primary register operation.
  • [43:0] 44 bit auxiliary values.

As commented, the communication is through the UART port, and each 4 bits are encoded in hex. Since UART uses the ASCII table for the characters, the following list shows the mapping between the ASCII characters and the hex value interpreted by the chip:

  • 1 ➜ 1
  • 2 ➜ 2
  • 3 ➜ 3
  • 4 ➜ 4
  • 5 ➜ 5
  • 6 ➜ 6
  • 7 ➜ 7
  • 8 ➜ 8
  • 9 ➜ 9
  • : ➜ A
  • ; ➜ B
  • < ➜ C
  • = ➜ D
  • > ➜ E
  • ? ➜ F

The sent data is buffered in a shift register, so in order to denote the end of the command, the ASCII character 0D (New line) needs to be sent. If you want to clear the buffered instruction, you can send the ASCII character 20 (Space), which clears the shift register.

Instruction Set

IWrite instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
IWriteWrites a logic 1 in the selected register
and is maintains it for the number of cycles denoted by the value of the Auxillary field.
000registercycles
IWriteWaits 1 Second and writes a logic 1 in
the selected selected register. The value is
maintained for a number of cycles denoted by the Auxillary field.
001registercycles



IRead instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
IReadReads the logic value in the selected register
and the read is delayed by Auxiliary number of cycles.
100registercycles



BWrite instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
BWriteWrites 8 bit value during one clock cycle.
The register and value are specified in the Auxiliary field.
011sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8] not used
[7:0] value for the registers
BWriteWaits 1 second and writes 8 bit value during one second.
The register and value are specified in the Auxiliary field.
111sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8] not used
[7:0] value for the registers



BRead instructions

TypeDescriptionOP Code [51:49]Primary Register [48:44]Auxillary [43:0]
BRriteReads 8 bit value during one clock cycle.
The register and value are specified in the Auxiliary field.
011sel register 7[43:39] sel register 6
[38:34] sel register 5
[33:29] sel register 4
[28:24] sel register 3
[23:19] sel register 2
[18:13] sel register 1
[13:9] sel register 0
[8:0] not used

Triple Redundancy Implementation

Block Description

Module Ports:

  • Input Ports
  • Output Ports

Caravel Connections

GPIO Connections

Logic Analyzer Probes

  • Input probes:

  • Output probes:

Wishbone Connection

User Maskable Interrupt Signals

Description of the Modules

Module List

Wishbone Description

Memory Map

Software Example

Available Tests