| commit | f68baeb9d91c310b36ba2cb5dce0f949e0957ed5 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sun Jan 09 08:43:57 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sun Jan 09 08:43:57 2022 -0800 |
| tree | e691d6c2b07780795fd2a08d09cbda126a12c9cc | |
| parent | 60631e41acc119ee43802be1fd05534b17fd4541 [diff] |
final gds oasis
This design is a radiation tolerant UART server that can be used for low level control of multiple input/output ports during a radiation testing campaign. The system features triple redundancy in order to ensure that the commands are properly executed.
In addition to simulation, the RTL design of the user project is verified also on a Xilinx Zybo Z7-20 FPGA using Vivado. The UART communication protocol is based on https://github.com/alexforencich/verilog-uart and its files are covered with the same open source license as the rest of the project (MIT).
This chip uses the UART port for main communication. This communication port is used to send instructions and receive the requested output. The input is a 52 bit word for communication. In order to fill up the word, the values are sent one by one via the UART port. The 52 bit are divided in this well defined sections:
As commented, the communication is through the UART port, and each 4 bits are encoded in hex. Since UART uses the ASCII table for the characters, the following list shows the mapping between the ASCII characters and the hex value interpreted by the chip:
The sent data is buffered in a shift register, so in order to denote the end of the command, the ASCII character 0D (New line) needs to be sent. If you want to clear the buffered instruction, you can send the ASCII character 20 (Space), which clears the shift register.
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| IWrite | Writes a logic 1 in the selected register and is maintains it for the number of cycles denoted by the value of the Auxillary field. | 000 | register | cycles |
| IWrite | Waits 1 Second and writes a logic 1 in the selected selected register. The value is maintained for a number of cycles denoted by the Auxillary field. | 001 | register | cycles |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| IRead | Reads the logic value in the selected register and the read is delayed by Auxiliary number of cycles. | 100 | register | cycles |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| BWrite | Writes 8 bit value during one clock cycle. The register and value are specified in the Auxiliary field. | 011 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8] not used [7:0] value for the registers |
| BWrite | Waits 1 second and writes 8 bit value during one second. The register and value are specified in the Auxiliary field. | 111 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8] not used [7:0] value for the registers |
| Type | Description | OP Code [51:49] | Primary Register [48:44] | Auxillary [43:0] |
|---|---|---|---|---|
| BRrite | Reads 8 bit value during one clock cycle. The register and value are specified in the Auxiliary field. | 011 | sel register 7 | [43:39] sel register 6 [38:34] sel register 5 [33:29] sel register 4 [28:24] sel register 3 [23:19] sel register 2 [18:13] sel register 1 [13:9] sel register 0 [8:0] not used |
Input probes:
Output probes:
