| /root/space_controller/run_test.sh |
| /root/space_controller/clean_run.sh |
| /root/space_controller/Makefile |
| /root/space_controller/make_complete.sh |
| /root/space_controller/make_sythesys.sh |
| /root/space_controller/docs/environment.yml |
| /root/space_controller/docs/Makefile |
| /root/space_controller/docs/source/index.rst |
| /root/space_controller/docs/source/conf.py |
| /root/space_controller/verilog/dv/Makefile |
| /root/space_controller/verilog/dv/la_test2/la_test2_tb.v |
| /root/space_controller/verilog/dv/la_test2/la_test2.c |
| /root/space_controller/verilog/dv/la_test2/Makefile |
| /root/space_controller/verilog/dv/la_test1/la_test1.c |
| /root/space_controller/verilog/dv/la_test1/Makefile |
| /root/space_controller/verilog/dv/la_test1/la_test1_tb.v |
| /root/space_controller/verilog/dv/io_ports/Makefile |
| /root/space_controller/verilog/dv/io_ports/io_ports_tb.v |
| /root/space_controller/verilog/dv/io_ports/io_ports.c |
| /root/space_controller/verilog/dv/mprj_stimulus/Makefile |
| /root/space_controller/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/space_controller/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/space_controller/verilog/dv/wb_port/wb_port_tb.v |
| /root/space_controller/verilog/dv/wb_port/Makefile |
| /root/space_controller/verilog/dv/wb_port/wb_port.c |
| /root/space_controller/verilog/rtl/uprj_netlists.v |
| /root/space_controller/verilog/rtl/user_proj_example.v |
| /root/space_controller/verilog/rtl/user_project_wrapper.v |
| /root/space_controller/verilog/rtl/controller/status_sender_data.v |
| /root/space_controller/verilog/rtl/controller/io_module.v |
| /root/space_controller/verilog/rtl/controller/pmu.v |
| /root/space_controller/verilog/rtl/controller/main_module.v |
| /root/space_controller/verilog/rtl/controller/control_module.v |
| /root/space_controller/verilog/rtl/controller/logic_control.v |
| /root/space_controller/verilog/rtl/controller/UART_SERVER/uart_rx.v |
| /root/space_controller/verilog/rtl/controller/UART_SERVER/uart.v |
| /root/space_controller/verilog/rtl/controller/UART_SERVER/uart_tx.v |
| /root/space_controller/verilog/rtl/controller/UART_SERVER/COPYING |
| /root/space_controller/sdf/user_proj_example.sdf |
| /root/space_controller/sdf/user_project_wrapper.sdf |
| /root/space_controller/sdc/user_project_wrapper.sdc |
| /root/space_controller/sdc/user_proj_example.sdc |
| /root/space_controller/openlane/Makefile |
| /root/space_controller/openlane/user_proj_example/config.json |
| /root/space_controller/openlane/user_proj_example/config.tcl |
| /root/space_controller/openlane/user_project_wrapper/config.json |
| /root/space_controller/openlane/user_project_wrapper/config.tcl |
| /root/space_controller/spef/user_project_wrapper.spef |
| /root/space_controller/spef/user_proj_example.spef |
