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  1. daf2108 final gds oasis by Jeff DiCorpo · 9 months ago main
  2. 1c86ab2 Completed check-in 3 with QSPI by Rameen Anwar · 10 months ago
  3. 5b92b43 Added files after placing filler cells and re run make by Rameen Anwar · 10 months ago
  4. 7b0d008 Fixed GDS for experiment 1 by Rameen Anwar · 10 months ago
  5. 79a8347 Added uncompressed def file for Azadi SoC by Rameen Anwar · 10 months ago

Azadi-III

License UPRJ_CI Caravel Build

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.