foundryslot-001PLL-based...: Time-based capacitive sensor interface using highly-digital custom building blocks.slot-002mpw5_cache: We have integrated a smaller version of the 4-way set associative 256B L1 cache as user project area in caravel SoC.slot-003Zero to ASIC...: Zero to ASIC course group submission MPW5.slot-004Zero to ASIC...: Zero to ASIC MPW2 rerun on MPW5.slot-005Zero to ASIC...: Zero to ASIC MPW3 rerun on MPW5.slot-006Zero to ASIC...: Zero to ASIC MPW4 rerun on MPW5.slot-007ActuatorController: A phased PWM controller for micro motor control.slot-008Microwatt MPW5: Microwatt is a 64 bit OpenPOWER core written in VHDL.slot-009armleo_gpio_mpw5: armleo_gpio is a input output IP that is designed to handle 12pF @ 100MHz.slot-010FABulous_eFPGA: Demonstration of the open FABulous eFPGA using the OpenLane flow.slot-011I2C Controller: I2C bus controller transmits 8-bit serial data to multiple targets.slot-012LBIST-MBIST: Logic BIST with Scan Chain to detect struck at fault MBIST with 4 Location Row Redundancy Support.slot-013Riscduino-DCore: Riscduino with Dual RISC V 32bit core.slot-014Riscduino-QCore: Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.slot-015high_speed_vco: 3GHz High Speed VCO.slot-016OpenFASOC-cryo-gen: Automated Test scribes for cryogenic PDK generation and SPICE models enhancements using OpenFASOC Project done in collaboration with NIST.slot-017Microwave Signal...: 2.87 GHz microwave signal generator with a small programmable sweep step size.slot-018PICO Design...: This project includes two different designs submitted as part of SSCS PICO-2021.slot-019ASK Modulator...: This design contains an ASK Modulator that outputs signals in the 2.slot-020Baseband...: An Automatic Gain Control (AGC) feedback-loop oriented towards baseband applications (0-600 MHz) without the need for integrated inductors.slot-021Azadi_III: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II.slot-022TIA for physic...: This project implements a low-noise high bandwidth (~1GHz) transimpedance amplifier (TIA).slot-023qf105: Lanai-based microcontroller, implemented in Bluespec.slot-024Coriolis Test...: VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be theoretically linux-capable.slot-025junga_soc_mpw5: Simple vexriscv based SoC.slot-026NAND Flash MPW-5: Small hand-drawn NAND flash array.slot-027kasirga-c0-mpw-5: RISC-V SoC.slot-028Delta-Sigma...: As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC, with a maximized digital and minimized analog content.slot-029WirelessEnergyHarvesting: Improving WEH systems through voltage boosting and component sharing.slot-030Raster_engine: An implementation of rasterization engine using Skywater 130 nm PDK.slot-031DDR3 SSTL Test: Test chip for a DDR3 SSTL driver.slot-032PSRAM Interface with PRNG: HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.slot-033ALU: Digital design that compares the ALU results.slot-0344ft4: an MCS-4 clone (4004, 4001, 4002).slot-035RNG CHAOS: In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.slot-036UETRV-ECore: UETRV-ECore: An embedded class RISC V based Motor Control SoC.slot-037Systolic_array: We design a 2-D systolic array architecture as shown in teh figure.slot-038ReRAM Test: Testing ReRAM structures.slot-039Pseudo-Secure Memory: SRAM based pseudo-secure memory.slot-040Asynchronous...: Asynchronous Fibonacci counter using two phase dual rail logic.