Coriolis Test...: VexRiscv+SPI flash+HyperRAM SoC built using Coriolis & PDKMaster - WIP designed to be theoretically linux-capable.

Clone this repo:

Branches

  1. 8750afc final gds oasis by Jeff DiCorpo · 2 years, 7 months ago main
  2. 1ba9509 Auto updated submodule references by Git bot · 2 years, 8 months ago
  3. 939e6ec Auto updated submodule references by Git bot · 2 years, 8 months ago
  4. 75a82a6 Auto updated submodule references by Git bot · 2 years, 8 months ago
  5. 1da7e52 Auto updated submodule references by Git bot · 2 years, 8 months ago

Amaranth+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

  • Minerva RV32IM CPU
  • 512 bytes SRAM
  • (Q)SPI flash for code and data memory using spimemio from picosoc
  • HyperRAM for RAM extension using a derivative of litehyperbus
  • 8-bit GPIO
  • UART, timer, and interrupt controller

Built using: