PSRAM Interface with PRNG: HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.

Clone this repo:


  1. 3e4b007 final gds oasis by Jeff DiCorpo · 1 year, 7 months ago main
  2. 29e4bd4 Touched up readme. by Steve Goldsmith · 1 year, 9 months ago
  3. fd08fc0 Re-harden user_project_example by Steve Goldsmith · 1 year, 9 months ago
  4. 88d3b27 Added SPDX and removed cover traces (beacause of pre-check; this seems not good) by Steve Goldsmith · 1 year, 9 months ago
  5. f0f7f38 First working version. by Steve Goldsmith · 1 year, 9 months ago

PSRAM Interface with PRNG

PSRAM and integration: Steve Goldsmith, Lead Instructor, Aurifex Labs,

PRNG: Zhenle Cao

Many thanks to Matt Venn!


PSRAM Interface

For this project I built a PSRAM interface.

Designed from the IS66/67WVH16M8ALL/BLL datasheet:

Includes programmable latency and post-transaction delay. For read synchronization, selectable between programmable latency or rwds strobe.


Thanks to Zhenle Cao for providing the random number generator. See:

Summary (quoted from Zhenle's project): This project as a ACORN (Additive Congruential Random Number) generator made to fit in the group tapeout submission as part of the Zero to ASIC Course. This project was implemented according to the information here: This ACORN generator is hardwired to have k = 16 and Modulus M = 2^12 (chosen due to the limitation on the number of GPIO output pins). However, it is highly scalable, and I was able to harden with at least k=16, M = 2^64. The area of the logic directly scales with k*M as the component that takes up the most space are the registers.


Instead of worrying about mucking up the tool with config and filenames, I just modified the example as little as possible.

Should be just these files (but diff to be sure):

  • verilog/rtl/user_proj_example.v
  • verilog/dv/la_test2_tb.v
  • verilog/dv/la_test2.c
  • openlane/user_proj_example/config.tcl
  • openlane/user_project_wrapper/macro.cfg

And added for unit testing with SymbiYosys

  • verilog/rtl/original/hyperram.v
  • verilog/rtl/unit_test/cover.sby

But I had to manually modify the original System Verilog that I had written to get hardening to work by removing always_ff, etc.


Testing was done in two parts

Unit Tests

Manual cover statements were visually inspected against the PSRAM datasheet.

Requires installing SymbiYosys:

To run: cd verilog/rtl/unit_test

sby cover.sby

To run again: rm -r cover && sby cover.sby

Inspect: gtkwave cover/engine_0/trace*.png

Tests include:

  • read
  • write
  • 2 reads
  • 2 writes
  • read and write

Caravel Test

To run:

make verify-la_test2-rtl

make verify-la_test2-gl

This only tests that the PSRAM state machine advances to state 2.