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  1. d4425fb final gds oasis by Jeff DiCorpo · 9 months ago main
  2. c4f0e55 change c0 die size by yct000 · 11 months ago
  3. 204c909 v4 by yct000 · 11 months ago
  4. f027045 add slow uart files by yct000 · 11 months ago
  5. 7f3c6cd modify rtl files for slow uart by yct000 · 11 months ago

Kasırga C0 RISC-V SoC

License UPRJ_CI Caravel Build

Table of contents

Overview

This repo contains the RISC-V based C0 SoC that utilizes caravel chip user space. C0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

C0 Block Diagram

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Key Features

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Prerequisites

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Running Full Chip Simulation

TBA

Hardening the Kasirga C0 using Openlane

TBA

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck