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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-027 / 204c909f9d1eb453ec18777528d78058428fe9c1
commit204c909f9d1eb453ec18777528d78058428fe9c1[log] [tgz]
authoryct000 <yahyacantugrul@gmail.com>Sat Mar 19 17:33:45 2022 +0300
committeryct000 <yahyacantugrul@gmail.com>Sat Mar 19 17:33:45 2022 +0300
tree99c24bbbf66ae79c376696b585bd8d791f4195b7
parentf027045bdf684ded3486ad77dd6a4d3414b45f53 [diff]
v4
22 files changed
tree: 99c24bbbf66ae79c376696b585bd8d791f4195b7
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Kasırga C0 RISC-V SoC

License UPRJ_CI Caravel Build

Table of contents

Overview

This repo contains the RISC-V based C0 SoC that utilizes caravel chip user space. C0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

C0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga C0 using Openlane

TBA

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck