commit	d4425fb2b22c348582d8e703e01a202a8afeb61c	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Sun May 01 01:23:57 2022 -0700
committer	Jeff DiCorpo <jeffdi@efabless.com>	Sun May 01 01:23:57 2022 -0700
tree	655379aa6e292ea2059edcd51862924e4d9e5afe
parent	c4f0e550fb347306a50025414ac1b6944216a86c [diff]

final gds oasis

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88 files changed

tree: 655379aa6e292ea2059edcd51862924e4d9e5afe

README.md

Kasırga C0 RISC-V SoC

Table of contents

Overview
K0 Block Diagram
Key Features
Prerequisites
Running Full Chip Simulation
Hardening the Kasirga K0 using Openlane
Checklist for Open-MPW Submission

Overview

This repo contains the RISC-V based C0 SoC that utilizes caravel chip user space. C0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.

C0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga C0 using Openlane

TBA

Checklist for Open-MPW Submission

✔️ The project repo adheres to the same directory structure in this repo.
✔️ The project repo contain info.yaml at the project root.
✔️ Top level macro is named user_project_wrapper.
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
✔️ The hardened Macros are LVS and DRC clean
✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
✔️ XOR check passes with zero total difference.
✔️ Openlane summary reports are retained under ./signoff/
✔️ The design passes the mpw-precheck