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  1. 500d847 final gds oasis by Jeff DiCorpo · 9 months ago main
  2. 3f16097 Update README.md by Veerendra S Devaraddi · 10 months ago
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  4. 8bbff15 Initial commit by Veerendra S Devaraddi · 10 months ago

Caravel User Project

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We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing ELement (PE) which takes in 3 inputs and produces an output. Each PE shifts the data of horizontally and vertically to the neighboring PEs every clock cycle. Systolic arrays access the memory only once, and all the PEs transfer the data to the nearby PEs, thus reducing the memory access. Specification: 5 horizontal inputs and 5 vertical inputs 5 diagonal inputs All 15 inputs are given the same input in our design Each input is 8 bits wide Clock: 100MHz Outputs: 5, which are 8 bits wide Operation being performed: Multiplication and Accumulation at each PE.