| commit | 3f1609702efa078f0f25a148bf17c1adf25db4b7 | [log] [tgz] |
|---|---|---|
| author | Veerendra S Devaraddi <43822985+vsdevaraddi@users.noreply.github.com> | Sun Mar 20 15:30:52 2022 +0530 |
| committer | GitHub <noreply@github.com> | Sun Mar 20 15:30:52 2022 +0530 |
| tree | bf153092218aa4445107b2184082d618e25b5958 | |
| parent | d57a3aafbe308729ed7aad0324705c8241a2cb95 [diff] |
Update README.md
We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing ELement (PE) which takes in 3 inputs and produces an output. Each PE shifts the data of horizontally and vertically to the neighboring PEs every clock cycle. Systolic arrays access the memory only once, and all the PEs transfer the data to the nearby PEs, thus reducing the memory access. Specification: 5 horizontal inputs and 5 vertical inputs 5 diagonal inputs All 15 inputs are given the same input in our design Each input is 8 bits wide Clock: 100MHz Outputs: 5, which are 8 bits wide Operation being performed: Multiplication and Accumulation at each PE.