Update README.md
diff --git a/README.md b/README.md
index 5d39f10..19d6acd 100644
--- a/README.md
+++ b/README.md
@@ -2,35 +2,12 @@
[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
-| :exclamation: Important Note |
-|-----------------------------------------|
-
-## Please fill in your project documentation in this README.md file
-
-Refer to [README](docs/source/quickstart.rst) for a quick start of how to use caravel_user_project
-
-Refer to [README](docs/source/index.rst) for this sample project documentation.
-Quick Launch for Designers
-
-## Dependencies
-
-- Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Apple Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header)
-
-## Running the simulation
-
-Assuming you already:
-- went throught the [quick start](https://github.com/efabless/caravel_user_project/blob/main/docs/source/quickstart.rst) for setting up your environemnt,
-- integrated your design into the user's wrapper and
-- hardenned your design as well as the user's wrapper (for GL simulation)
-
-````
-make simenv
-SIM=RTL make verify-<dv-test>
-# OR
-SIM=GL make verify-<dv-test>
-````
-``<dv-test>``: io_ports, mprj_stimulus, la_test1, la_test2 or wb_port.
-
-# For advanced users
-
-## Simulation Environment Setup
+We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing ELement (PE) which takes in 3 inputs and produces an output. Each PE shifts the data of horizontally and vertically to the neighboring PEs every clock cycle. Systolic arrays access the memory only once, and all the PEs transfer the data to the nearby PEs, thus reducing the memory access.
+Specification:
+5 horizontal inputs and 5 vertical inputs
+5 diagonal inputs
+All 15 inputs are given the same input in our design
+Each input is 8 bits wide
+Clock: 100MHz
+Outputs: 5, which are 8 bits wide
+Operation being performed: Multiplication and Accumulation at each PE.
