| commit | d57a3aafbe308729ed7aad0324705c8241a2cb95 | [log] [tgz] |
|---|---|---|
| author | vsdevaraddi <veerendra.s@iiitb.ac.in> | Sun Mar 20 15:10:01 2022 +0530 |
| committer | vsdevaraddi <veerendra.s@iiitb.ac.in> | Sun Mar 20 15:10:01 2022 +0530 |
| tree | 34d44f0e331207017def0b07a97fd0872af70665 | |
| parent | 8bbff1567d1ed53bf0d7ca0af65515881c796be5 [diff] |
first commit
| :exclamation: Important Note |
|---|
Refer to README for a quick start of how to use caravel_user_project
Refer to README for this sample project documentation. Quick Launch for Designers
Assuming you already:
make simenv SIM=RTL make verify-<dv-test> # OR SIM=GL make verify-<dv-test>
<dv-test>: io_ports, mprj_stimulus, la_test1, la_test2 or wb_port.
