Keeping your data secure. This project aims to secure data from adversaries. It has inherent SRAM to keep the data safe and they are kept as not plaintext but ciphered. We got 5 macros inherently in order to accomplish our goal. Below section will be described those macros briefly.
TRNG - True random number generator. Ring oscillator macro which is one of the inner macros of caravel core, is used. In this macro, delay buffers are used instead of not gates. It can be also used as key generator for AES.
SPI - SPI pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via SPI.
UART - UART pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via UART.
AES - Cipher plaintext to keep data safe in SRAM.
SRAM - Our precious. Its 1KB.
All these macros are in located in the
sudo apt update sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add - sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable" sudo apt update apt-cache policy docker-ce sudo apt install docker-ce #Add User Name to docker sudo usermod -aG docker <your user name> # Reboot the system to enable the docker setup
git clone -b mpw-5c https://github.com/efabless/caravel_user_project
export CARAVEL_ROOT=<Caravel Installed Path> export PDK_ROOT=<PDK Installed PATH> export UPRJ_ROOT=<Caravel User Project Installed Path> export OPENLANE_ROOT=<OpenLane Installed Path> export OPENLANE_IMAGE_NAME=efabless/openlane:2022.02.23_02.50.41
source ~/.bashrc cd $UPRJ_ROOT make install # install pdk. pdk with sram, openlane. caravel and mgmt core
A subdirectory for each macro in your project under openlane/ directory, each subdirectory should include openlane configuration files for the macro
make <module_name> make user_project_wrapper
# you can then run RTL simulations using make verify-<testbench-name>-rtl # or GL simulation using make verify-<testbench-name>-gl # for example make verify-wb_port-rtl
make precheck make run-precheck
Mbist Controller flow uses Openlane tool sets.
yosys - Performs RTL synthesis
abc - Performs technology mapping
OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
ioplacer - Places the macro input and output ports
pdn - Generates the power distribution network
tapcell - Inserts welltap and decap cells in the floorplan
RePLace - Performs global placement
Resizer - Performs optional optimizations on the design
OpenPhySyn - Performs timing optimizations on the design
OpenDP - Perfroms detailed placement to legalize the globally placed components
TritonCTS - Synthesizes the clock distribution network (the clock tree)
FastRoute - Performs global routing to generate a guide file for the detailed router
CU-GR - Another option for performing global routing.
TritonRoute - Performs detailed routing
SPEF-Extractor - Performs SPEF extraction
Magic - Streams out the final GDSII layout file from the routed def
Klayout - Streams out the final GDSII layout file from the routed def as a back-up
Magic - Performs DRC Checks & Antenna Checks
Klayout - Performs DRC Checks
Netgen - Performs LVS Checks
CVC - Performs Circuit Validity Checks