Clone this repo:

Branches

  1. 1eb78c1 final gds oasis by Jeff DiCorpo · 9 months ago main
  2. 5033b0c added pic by nguyendao-uom · 11 months ago
  3. 1f28d81 added PDN by nguyendao-uom · 11 months ago
  4. 603d248 updated decap_12 by nguyendao-uom · 11 months ago
  5. 0cf2f96 updated power pins by nguyendao-uom · 11 months ago

Caravel User Project

License UPRJ_CI Caravel Build

Demonstration of the fully open FABulous eFPGA using the OpenLane flow.

This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 576x LUT4s (12x6 CLBs), 48x LUT5s (12x1 RegFiles), 6x DSPs and 6x BRAMs (6x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version.

The fabrics were fully implemented using the OpenLane flow then integrated onto eFabless caravel.