| commit | 1eb78c12e13701cdc6078476105f50e9b9cb7077 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sat Apr 30 19:46:16 2022 -0700 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sat Apr 30 19:46:16 2022 -0700 |
| tree | e1e7eb4f19a160fa9f97dc52cabb40f079bb56a0 | |
| parent | 5033b0c8917599cdf3e28400e4d4714259a8654b [diff] |
final gds oasis
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 576x LUT4s (12x6 CLBs), 48x LUT5s (12x1 RegFiles), 6x DSPs and 6x BRAMs (6x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version.
The fabrics were fully implemented using the OpenLane flow then integrated onto eFabless caravel.
