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/root/fabulous_efpga/Makefile
/root/fabulous_efpga/docs/Makefile
/root/fabulous_efpga/docs/environment.yml
/root/fabulous_efpga/docs/source/conf.py
/root/fabulous_efpga/docs/source/index.rst
/root/fabulous_efpga/docs/source/quickstart.rst
/root/fabulous_efpga/openlane/user_proj_example/config.json
/root/fabulous_efpga/openlane/user_proj_example/config.tcl
/root/fabulous_efpga/openlane/user_project_wrapper/config.json
/root/fabulous_efpga/openlane/user_project_wrapper/config.tcl
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/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/E_CPU_IO.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/E_CPU_IO_bot.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/LUT4AB.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_DSP.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_RAM_IO.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_single.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_single2.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/RAM_IO.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/RegFile.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_DSP.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_RAM_IO.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_single.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_single2.lib
/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/W_CPU_IO.lib
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/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/flexbex_ibex_core.lib
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/root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/sky130_lib/sky130_fd_sc_hd__ff_n40C_1v95.lib
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/root/fabulous_efpga/verilog/dv/Makefile
/root/fabulous_efpga/verilog/dv/io_ports/Makefile
/root/fabulous_efpga/verilog/dv/io_ports/io_ports.c
/root/fabulous_efpga/verilog/dv/io_ports/io_ports_tb.v
/root/fabulous_efpga/verilog/dv/la_test1/Makefile
/root/fabulous_efpga/verilog/dv/la_test1/la_test1.c
/root/fabulous_efpga/verilog/dv/la_test1/la_test1_tb.v
/root/fabulous_efpga/verilog/dv/la_test2/Makefile
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/root/fabulous_efpga/verilog/dv/la_test2/la_test2_tb.v
/root/fabulous_efpga/verilog/dv/mprj_stimulus/Makefile
/root/fabulous_efpga/verilog/dv/mprj_stimulus/mprj_stimulus.c
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/root/fabulous_efpga/verilog/dv/wb_port/Makefile
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/root/fabulous_efpga/verilog/includes/includes.gl+sdf.caravel_user_project
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/root/fabulous_efpga/verilog/includes/includes.rtl.caravel_user_project
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/root/fabulous_efpga/verilog/rtl/ConfigFSM.v
/root/fabulous_efpga/verilog/rtl/Config_access.v
/root/fabulous_efpga/verilog/rtl/Frame_Data_Reg_Pack.v
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/root/fabulous_efpga/verilog/rtl/bitbang.v
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