| /root/fabulous_efpga/Makefile |
| /root/fabulous_efpga/docs/Makefile |
| /root/fabulous_efpga/docs/environment.yml |
| /root/fabulous_efpga/docs/source/conf.py |
| /root/fabulous_efpga/docs/source/index.rst |
| /root/fabulous_efpga/docs/source/quickstart.rst |
| /root/fabulous_efpga/openlane/user_proj_example/config.json |
| /root/fabulous_efpga/openlane/user_proj_example/config.tcl |
| /root/fabulous_efpga/openlane/user_project_wrapper/config.json |
| /root/fabulous_efpga/openlane/user_project_wrapper/config.tcl |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/BRAM.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/DSP.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/E_CPU_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/E_CPU_IO_bot.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/LUT4AB.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_DSP.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_RAM_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_single.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/N_term_single2.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/RAM_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/RegFile.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_DSP.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_RAM_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_single.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/S_term_single2.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/W_CPU_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/W_CPU_IO_bot.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/W_IO.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/cus_tg_mux41_buf.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/flexbex_ibex_core.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/ibex_core.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/ibex_top.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/sky130_lib/sky130_fd_sc_hd__ff_n40C_1v95.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/sky130_lib/sky130_fd_sc_hd__ss_100C_1v60.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/sky130_lib/sky130_fd_sc_hd__tt_025C_1v80.lib |
| /root/fabulous_efpga/openlane/user_project_wrapper/macros/lib/sky130_lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib |
| /root/fabulous_efpga/verilog/dv/Makefile |
| /root/fabulous_efpga/verilog/dv/io_ports/Makefile |
| /root/fabulous_efpga/verilog/dv/io_ports/io_ports.c |
| /root/fabulous_efpga/verilog/dv/io_ports/io_ports_tb.v |
| /root/fabulous_efpga/verilog/dv/la_test1/Makefile |
| /root/fabulous_efpga/verilog/dv/la_test1/la_test1.c |
| /root/fabulous_efpga/verilog/dv/la_test1/la_test1_tb.v |
| /root/fabulous_efpga/verilog/dv/la_test2/Makefile |
| /root/fabulous_efpga/verilog/dv/la_test2/la_test2.c |
| /root/fabulous_efpga/verilog/dv/la_test2/la_test2_tb.v |
| /root/fabulous_efpga/verilog/dv/mprj_stimulus/Makefile |
| /root/fabulous_efpga/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/fabulous_efpga/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/fabulous_efpga/verilog/dv/wb_port/Makefile |
| /root/fabulous_efpga/verilog/dv/wb_port/wb_port.c |
| /root/fabulous_efpga/verilog/dv/wb_port/wb_port_tb.v |
| /root/fabulous_efpga/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/fabulous_efpga/verilog/includes/includes.gl.caravel_user_project |
| /root/fabulous_efpga/verilog/includes/includes.rtl.caravel_user_project |
| /root/fabulous_efpga/verilog/rtl/Config.v |
| /root/fabulous_efpga/verilog/rtl/ConfigFSM.v |
| /root/fabulous_efpga/verilog/rtl/Config_access.v |
| /root/fabulous_efpga/verilog/rtl/Frame_Data_Reg_Pack.v |
| /root/fabulous_efpga/verilog/rtl/Frame_Select_Pack.v |
| /root/fabulous_efpga/verilog/rtl/bitbang.v |
| /root/fabulous_efpga/verilog/rtl/config_UART.v |
| /root/fabulous_efpga/verilog/rtl/defines.v |
| /root/fabulous_efpga/verilog/rtl/eFPGA_v3_top_sky130.v |
| /root/fabulous_efpga/verilog/rtl/fabric_DSP_tile.v |
| /root/fabulous_efpga/verilog/rtl/models_pack.v |
| /root/fabulous_efpga/verilog/rtl/user_project_wrapper.v |
| /root/fabulous_efpga/verilog/rtl/BB/BlockRAM_1KB.v |
| /root/fabulous_efpga/verilog/rtl/BB/DSP_bot_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/DSP_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/DSP_top_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/LUT4AB_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/N_term_DSP_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/N_term_RAM_IO_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/N_term_single2_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/N_term_single_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/RAM_IO_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/RegFile_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/S_term_DSP_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/S_term_RAM_IO_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/S_term_single2_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/S_term_single_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/W_IO_tile.v |
| /root/fabulous_efpga/verilog/rtl/BB/fabric_DSP_tile.v |