| commit | 5033b0c8917599cdf3e28400e4d4714259a8654b | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Tue Mar 22 11:34:47 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Tue Mar 22 11:34:47 2022 +0000 |
| tree | 7e9ed125c39fd117e493db5d107c85b0845df0ee | |
| parent | 1f28d8103ca78feabf0947fdb17966ce90a2829a [diff] |
added pic
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 576x LUT4s (12x6 CLBs), 48x LUT5s (12x1 RegFiles), 6x DSPs and 6x BRAMs (6x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version.
The fabrics were fully implemented using the OpenLane flow then integrated onto eFabless caravel.
