added pic
diff --git a/README.md b/README.md index 324f253..32b35e0 100644 --- a/README.md +++ b/README.md
@@ -4,10 +4,11 @@ Demonstration of the fully open FABulous eFPGA using the OpenLane flow. -This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version. +This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by [FABulous framework](https://github.com/FPGA-Research-Manchester/FABulous). The fabric consists of 576x LUT4s (12x6 CLBs), 48x LUT5s (12x1 RegFiles), 6x DSPs and 6x BRAMs (6x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version. + +The fabrics were fully implemented using the [OpenLane flow](https://github.com/The-OpenROAD-Project/OpenLane.git) then integrated onto [eFabless caravel](https://github.com/efabless/caravel_user_project.git). <p align="center"> - <img src="./docs/source/eFPGA_ver3.png" width="50%" height="50%"> + <img src="./docs/source/mpw5_open_eFPGA.png" width="50%" height="50%"> </p> -Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/docs/source/mpw5_open_eFPGA.png b/docs/source/mpw5_open_eFPGA.png new file mode 100644 index 0000000..25b1cf1 --- /dev/null +++ b/docs/source/mpw5_open_eFPGA.png Binary files differ
